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1/85 preliminary data january 2000 m88 family in-system programmable (isp) multiple-memory and logic flash+psd systems for mcus n single supply voltage: 5v 10% for m88x3fxy 3 v (+20/10%) for m88x3fxw n fast access time: 90nsor150nsat5v 150 ns at 3 v n 1 mbit (128k x 8) flash memory 8 uniform blocks of 16k x 8 each n a second non-volatile memory: 256 kbit (32k x 8) eeprom (for m8813f1x) or flash memory (for m88x3f2x) 4 uniform blocks n 16 kbit (2k x 8) sram for m8813fxx (not available on m8803fxx) n over 3,000 gates of pld n reconfigurable i/o ports n jtag interface n programmable power management n high endurance: 100,000 erase/write cycles of flash memory 10,000 erase/write cycles of eeprom 1,000 erase/write cycles of pld figure 1. logic diagram ai02856 16 ad0-ad15 pc0-pc7 v cc flash+psd v ss 8 pd0-pd2 3 pb0-pb7 8 pa0-pa7 8 3 cntl0- cntl2 reset table 1. signal names pa0-pa7 port-a data lines pb0-pb7 port-b data lines pc0-pc7 port-c data lines pc2 = voltage stand-by pd0-pd2 port-d data lines ad0-ad15 address/data lines cntl0-cntl2 control lines cntl1 = clock in reset reset v cc supply voltage v ss ground plcc52 (k) pqfp52 (t)
m88 family 2/85 figure 2a. plcc connections pb0 pb1 pb2 pb3 pb4 pb5 gnd pb6 pb7 cntl1 cntl2 reset cntl0 pa7 pa6 pa5 pa4 pa3 gnd pa2 pa1 pa0 ad0 ad1 ad2 ad3 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 v cc ad7 ad6 ad5 ad4 pd2 pd1 pd0 pc7 pc6 pc5 pc4 v cc gnd pc3 pc2 pc1 pc0 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 32 33 47 48 49 50 51 52 1 2 3 4 5 6 7 ai02857 figure 2b. pqfp connections 39 ad15 38 ad14 37 ad13 36 ad12 35 ad11 34 ad10 33 ad9 32 ad8 31 v cc 30 ad7 29 ad6 28 ad5 27 ad4 pd2 pd1 pd0 pc7 pc6 pc5 pc4 v cc gnd pc3 pc2 pc1 pc0 1 2 3 4 5 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 pb0 pb1 pb2 pb3 pb4 pb5 gnd pb6 pb7 cntl1 cntl2 reset cntlo 14 15 16 17 18 19 20 21 22 23 24 25 26 pa7 pa6 pa5 pa4 pa3 gnd pa2 pa1 pa0 ad0 ad1 ad2 ad3 ai02858 table 2. product range 1 note: 1. all products support: jtag serial isp, mcu parallel isp, isp flash memory, isp cpld, security features, power management unit (pmu), automatic power down (apd) 2. all devices with sram may be backed up using an external battery. part number sram 2 flash program store i/o ports 2nd nvm (boot area) voltage range access time m813f1y 16 kbit 1 mbit 27 256 kbit eeprom 4.5-5.5 v 90 ns or 150 ns m813f2y 16 kbit 1 mbit 27 256 kbit flash m813f3y 16 kbit 1 mbit 27 m803f2y 1 mbit 27 256 kbit flash m803f3y 1 mbit 27 m813f1w 16 kbit 1 mbit 27 256 kbit eeprom 2.7-3.6 v 150 ns m813f2w 16 kbit 1 mbit 27 256 kbit flash m813f3w 16 kbit 1 mbit 27 m803f2w 1 mbit 27 256 kbit flash m803f3w 1 mbit 27 description the m88x3fxx flash+psd family of memory systems for microcontrollers (mcus) brings in- system-programmability (isp) to flash memory and programmable logic. the result is a simple and flexible solution for embedded designs. m88x3fxx flash+psd devices combine many of the peripheral functions found in mcu based applications. m88x3fxx flash+psd devices feature an optimized amicrocontroller macrocello logic architecture called the macrocell. the macrocell was created to address the unique requirements of embedded system designs. it allows direct connection between the system address/data bus, and the internal psd registers, to simplify communication between the mcu and other supporting devices. the m88x3fxx flash+psd family includes a jtag serial programming interface, to allow in- system-programming of the entire device. this feature reduces development time, simplifies the manufacturing flow, and dramatically lowers the cost of field upgrades. using st's special fast- jtag programming, a design can be rapidly programmed into the m88x3fxx flash+psd. the innovative m88x3fxx flash+psd family solves key problems faced by designers when
3/85 m88 family figure 3. m88x3fxx flash+psd block diagram decode pld page reg flash memory eight blocks 1mbits total sram scratch pad 16 kbits 24 input macrocell (port a,b,c) macrocell alloc. pt alloc. pmu programmable i/o port programmable i/o port programmable i/o port programmable i/o port i/o ports direct read of macrocell 73 73 pld input bus device security mcu control interface mcu address/data control rd/ wr/ ad0-ad7 a8-a15 8 mcu address / data / control bus pa0-pa7 pb0-pb7 pd0-pd2 pc0-pc7 16 output macrocell isp cpld 3cs 16 vstdby/i/o (pc2) embedded algorithm command registers isp loader configuration, pld, & flash memory flash or eeprom four sectors 256 kbits total sector select boot periph. + i/o sel sram jtag serial channel clkin/pd1 output macrocell feedback, input macrocell & input ports direct read & write of macrocell (pc0-pc1), (pc3-pc6) ai02861c sometimes computers try to be too clever for their own good. take this illustration for instance. just because so many of the labels are rotated through ninety degrees, framemaker seems to want to insist on telling the postscript file that i would find it more convenient to see this page displayed in landscape, rotated by ninety degrees. well i wouldn't. so i am putting in all this text just to weight the average in this direction.
m88 family 4/85 managing discrete flash memory devices, such as: in-system first-time programming complex address decoding concurrent flash or eeprom programming. the m88x3fxx flash+psd's serial jtag interface allows in-system-programming and eliminates the need for a boot eprom or flash memory, or an external programmer. to simplify flash memory updates, some members of the family perform program execution out of a secondary eeprom (for the m8813f1x) or flash memory (for the m88x3f2x) while the main flash memory is being updated. this solution avoids the complicated hardware and software overhead necessary to implement in-system flash memory updates. st makes available a software development tool, psdsoft, that generates ansi-c compliant code for use with your target mcu. this code allows you to manipulate the non-volatile memory (nvm) within the psd. code examples are also provided for: flash memory isp via the uart of the host mcu memory paging to execute code across several psd memory pages loading, reading, and manipulation of psd macrocells by the mcu. key features n a simple interface to 8-bit microcontrollers, without the need for external glue-logic. the bus interface logic uses the control signals generated by the microcontroller when the address is decoded and a read or write is performed. the mcu families supported include: intel 8031, 80196, 80186, 80c251, and 80386ex motorola 68hc11, 68hc16, 68hc12, and 683xx philips 8031 and 8051xa zilog z80 and z8 neuron ? 3150 chip ? . n internal 1 mbit (128k x 8) flash memory. this is the main flash memory. it is divided into eight equal-sized blocks that can be accessed with user-specified addresses. n optional internal secondary 256 kbit (32k x 8) eeprom or flash boot memory. this is divided into four equal-sized blocks that can be accessed with user-specified addresses. the main flash memory can be updated concurrently while the secondary memory is executing code. n optional 16 kbit (2k x 8) scratch-pad sram. its contents can be protected from a power failure by connecting an external battery. table 3. absolute maximum ratings 1 note: 1. except for the rating aoperating temperature rangeo, stresses above those listed in the table aabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability . refer also to the st sure program and other relevant quality documents. 2. mil-std-883c, 3015.7 (100 pf, 1500 w ) 3. for the m88x3fxy, 5 v range only. symbol parameter value unit t a ambient operating temperature industrial -40 to 85 c commercial 0 to 70 c t stg storage temperature -65 to 125 c t lead lead temperature during soldering t.b.c. c v cc supply voltage 0.6 to 7 3 v v pp device programmer supply voltage 0.6 to 14 3 v v io input or output range (q = v oh or hi-z) 0.6 to 7 3 v v esd electrostatic discharge voltage (human body model) 2 2000 v
5/85 m88 family n optional 64 byte one time programmable (otp) memory (on the m8813f1x) that can be used for product configuration and calibration. n cpld with 16 output macrocells (omcs) and 24 input macrocells (imcs). the cpld may be used to implement efficiently a variety of logic functions for internal and external control. examples include state machines, loadable shift registers, and loadable counters. n decode pld (dpld) that decodes address for selection of internal memory blocks. the dpld can also be used to generate external chip selects. n 27 individually configurable i/o port pins that can be used for the following functions: mcu i/os pld i/os latched mcu address output special function i/os 16 of the i/o ports may be configured as open-drain outputs. n stand-by current as low as 50 m a for 5 v devices, 25 m a for 3 v devices. n built-in jtag compliant serial port allows full- chip in-system programmability (isp). with it, you can program a blank device or reprogram a device in the factory or the field. n internal page register that can be used to expand the microcontroller address space by a factor of 256. n internal programmable power management unit (pmu) that supports a low power mode called power down mode. the pmu can automatically detect a lack of microcontroller activity and put the m88x3fxx flash+psd into power down mode. general information the m88x3fxx flash+psd architecture allows in-system programming of all memory, pld logic and device configuration. the embedded input and output macrocells enable efficient implementation of user defined logic functions that require both software and hardware interaction. the devices eliminate the need for discrete `glue' logic, and allow the development of entire systems using only a few highly integrated devices. m88x3fxx flash+psd family all m88x3fxx flash+psd devices provide the base features: 1 mbit main flash memory, jtag port, cpld, dpld, power management, and twenty-seven i/o pins. some of the members of the m88x3fxx flash+psd family add to this set of basic features: n m8813fxx adds 16 kbit (2k x 8) sram to the base feature set. n m8813f1x adds 256 kbit (32k x 8) eeprom to the base feature set. it also adds 64 bytes of otp memory for any use (product serial number, calibration constants, etc.). once written, the otp memory can never be altered. n m88x3f2x adds a secondary 256 kbit (32k x 8) flash memory to the base feature set. these independent memories can operate concurrently with each other and with the main flash memory. table 2 summarizes all the devices in the m88x3fxx flash+psd family. m88x3fxx flash+psd architectural overview m88x3fxx flash+psd devices contain several major functional blocks. figure 3 shows the architecture of the m88x3fxx flash+psd device family. the functions of each block are described briefly in the following sections. many of the blocks perform multiple functions and are user configurable. memory each of the memories is briefly discussed in the following paragraphs. a more detailed discussion can be found in the section entitled am88 family functional blockso, on page 12. the 1 mbit (128k x 8) flash memory is the main memory of the m88x3fxx flash+psd. it is divided into eight equally-sized blocks that are individually selectable. the optional 256 kbit (32k x 8) eeprom or flash memory is divided into four equally-sized blocks. each block is individually selectable. the optional 16 kbit (2k x 8) sram is intended for use as a scratch-pad memory or as an extension to the microcontroller sram. if an external battery is connected to the m88x3fxx flash+psd's vstby pin, data will be retained in the event of a power failure. each block of memory can be located in a different address space as defined by the user. the access times for all memory types includes the address latching and dpld decoding time.
m88 family 6/85 page register the eight-bit page register expands the address range of the microcontroller by up to 256 times. the paged address can be used as part of the address space to access external memory and peripherals, or internal memory and i/o. the page register can also be used to change the address mapping of blocks of flash memory into different memory spaces for in-circuit reprogramming. plds the device contains two pld blocks, each optimized for a different function, as shown in table 4. the functional partitioning of the plds reduces power consumption, optimizes cost/ performance, and eases design entry. the decode pld (dpld) is used to decode addresses and to generate chip selects for the m88x3fxx flash+psd internal memory and registers. the cpld can implement user-defined logic functions. the dpld has combinatorial outputs. the cpld has 16 output macrocells and 3 combinatorial outputs. the m88x3fxx flash+psd also has 24 input macrocells that can be configured as inputs to the plds. the plds receive their inputs from the pld input bus and are differentiated by their output destinations, number of product terms, and macrocells. the plds consume minimal power. the speed and power consumption of the pld is controlled by the turbo bit in the pmmr0 register and other bits in the pmmr2 registers. these registers are set by the microcontroller at run-time. there is a slight penalty to pld propagation time when invoking the power management features. i/o ports the m88x3fxx flash+psd has 27 i/o pins distributed over the four ports (port a, b, c, and d). each i/o pin can be individually configured for different functions. ports a, b, c and d can be configured as standard mcu i/o ports, pld i/o, or latched address outputs for microcontrollers using multiplexed address/data buses. the jtag pins can be enabled on port c for in- system programming (isp). ports a and b can also be configured as a data port for a non-multiplexed bus or multiplexed address/data bus for certain types of 8-bit microcontrollers. microcontroller bus interface the m88x3fxx flash+psd easily interfaces with most 8-bit microcontrollers that have either multiplexed or non-multiplexed address/data buses. the device is configured to respond to the microcontroller's control signals, which are also used as inputs to the plds. where there is a requirement to use a 16-bit data bus to interface to a 16-bit microcontroller, two psds must be used. the section entitled amicrocontroller interface exampleso, on page 35, contains microcontroller interface examples. table 4. pld i/o name abbreviation inputs outputs product terms decode pld dpld 73 17 42 complex pld cpld 73 19 140 table 5. jtag signals on port c port c pins jtag signal pc0 tms pc1 tck pc3 tstat pc4 terr pc5 tdi pc6 tdo table 6. methods of programming different functional blocks of the m88 family functional block jtag programming device programmer in-system parallel programming main flash memory yes yes yes optional eeprom/flash boot memory yes yes yes pld array (dpld and cpld) yes yes no psd configuration yes yes no optional otp row no yes yes
7/85 m88 family jtag port in-system programming can be performed through the jtag pins on port c. this serial interface allows complete programming of the entire m88x3fxx flash+psd device. a blank device can be completely programmed. the jtag signals (tms, tck, tstat, terr, tdi, tdo) can be multiplexed with other functions on port c. table 5 indicates the jtag signals pin assignments. four-pin jtag is also fully supported. in-system programming using the jtag signals on port c, the entire m88x3fxx flash+psd device can be programmed or erased without the use of the microcontroller. the main flash memory can also be programmed in-system by the microcontroller executing the programming algorithms out of the optional eeprom, flash boot memory, or sram. the optional eeprom or flash boot memory can be programmed the same way by executing out of the main flash memory. the pld logic or other m88x3fxx flash+psd configuration can be programmed through the jtag port or a device programmer. table 6 indicates which programming methods can program different functional blocks of the m88x3fxx flash+psd. power management unit the power management unit (pmu) in the m88x3fxx flash+psd gives the user control of the power consumption on selected functional blocks based on system requirements. the pmu includes an automatic power down unit (apd) that will turn off device functions due to microcontroller inactivity. the apd unit has a power down mode that helps reduce power consumption. the m88x3fxx flash+psd also has some bits that are configured at run-time by the mcu to reduce power consumption of the cpld. the turbo bit in the pmmr0 register can be turned off and the cpld will latch its outputs and go to sleep until the next transition on its inputs. additionally, bits in the pmmr2 register can be set by the mcu to block signals from entering the cpld to reduce power consumption. see the section entitled apower managemento, on page 47. figure 4. psdsoft development tools psd configuration psd fitter psd simulator psd programmer *.obj file pld description configure mcu bus interface and other psd attributes logic synthesis and fitting psdsilos iii device simulation (optional) psdpro, or flashlink (jtag) address translation and memory mapping psdabel modify abel template file or generate new file psd tools generate c code specific to psd functions user's choice of microcontroller compiler/linker *.obj and *.svf files available for 3rd party programmers (conventional or jtag-isc) firmware hex or s-record format ai02862
m88 family 8/85 development system the m88x3fxx flash+psd family is supported by the windows-based psdsoft development system. the psdsoft design flow is shown in figure 4. the pld design entry is done using psdabel, which creates a minimized logic implementation, and provides logic simulation of the plds. the m88x3fxx flash+psd mcu bus interface and i/o port configuration are entered in psd configuration. psdsoft can generate ansi c functions specific to the psd. the user can merge these c functions with their own, and then compile and link it using any embedded c compiler on the market. psd fitter is comprised of a fitter and address translator. it generates a programming data file (.obj) based on psd configuration data, the psdabel file, and the microcontroller firmware. the object file can be downloaded to a table 7. pin description pin name pin 1 type description adio0-7 30-37 i/o this is the lower address/data port. connect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect ad[0:7] to this port. 2. if your mcu does not have a multiplexed address/data bus, or you are using an 80c251 in page mode, connect a[0:7] to this port. 3. if you are using an 80c51xa in burst mode, connect a4/d0 through a11/d7 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks was selected. the addresses on this port are passed to the plds. adio8-15 39-46 i/o this is the upper address/data port. connect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect a[8:15] to this port. 2. if your mcu does not have a multiplexed address/data bus, connect a[8:15] to this port. 3. if you are using an 80c251 in page mode, connect ad[8:15] to this port. 4. if you are using an 80c51xa in burst mode, connect a12/d8 through a19/d15 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks was selected. the addresses on this port are passed to the plds. cntl0 47 i the following control signals can be connected to this port, based on your mcu: 1. wr e active-low write input. 2. r_w e active-high read/active low write input. this port is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl1 50 i the following control signals can be connected to this port, based on your mcu: 1. rd e active-low read input. 2. e e e clock input. 3. ds e active-low data strobe input. 4. psen e connect psen to this port when it is being used as an active-low read signal. for example, when the 80c251 outputs more than 16 address bits, psenis actually the read signal. this port is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl2 49 i this port can be used to input the psen (program select enable) signal from any mcu that uses this signal for code exclusively. if your mcu does not output a program select enable signal, this port can be used as a generic input. this port is connected to the plds. reset 48 i active low reset input. resets i/o ports, pld macrocells and some of the configuration registers. must be active at power up.
9/85 m88 family pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 29 28 27 25 24 23 22 21 i/o these pins make up port a. these port pins are configurable and can have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. cpld macrocell (mcellab0-7) outputs. 3. inputs to the plds. 4. latched address outputs (see table 8). 5. address inputs. for example, pa0-3 could be used for a[0:3] when using an 80c51xa in burst mode. 6. as the data bus inputs d[0:7] for non-multiplexed address/data bus mcus. 7. d0/a16-d3/a19 in m37702m2 mode. 8. peripheral i/o mode. note: pa0-3 can only output cmos signals with an option for high slew rate. however, pa4-7 can be configured as cmos or open drain outputs. pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 7 6 5 4 3 2 52 51 i/o these pins make up port b. these port pins are configurable and can have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. cpld macrocell (mcellab0-7 or mcellbc0-7) outputs. 3. inputs to the plds. 4. latched address outputs (see table 8). note: pb0-3 can only output cmos signals with an option for high slew rate. however, pb4-7 can be configured as cmos or open drain outputs. pc0 20 i/o pc0 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. cpld macrocell (mcellbc0) output. 3. input to the plds. 4. tms input 2 for the jtag interface. this pin can be configured as a cmos or open drain output. pc1 19 i/o pc1 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. cpld macrocell (mcellbc1) output. 3. input to the plds. 4. tck input 2 for the jtag interface. this pin can be configured as a cmos or open drain output. pc2 18 i/o pc2 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. cpld macrocell (mcellbc2) output. 3. input to the plds. 4. v stby e sram stand-by voltage input for sram battery backup. this pin can be configured as a cmos or open drain output. pc3 17 i/o pc3 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. cpld macrocell (mcellbc3) output. 3. input to the plds. 4. tstat output 2 for the jtag interface. 5. ready/busy output for in-system parallel programming. this pin can be configured as a cmos or open drain output. pc4 14 i/o pc4 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. cpld macrocell (mcellbc4) output. 3. input to the plds. 4. terr output 2 for the jtag interface. 5. v baton e battery backup indicator output. goes high when power is being drawn from an external battery. this pin can be configured as a cmos or open drain output. pin name pin 1 type description
m88 family 10/85 note: 1. the pin numbers in this table are for the plcc package only. see the package information, on page 79 onwards, for pin numbers on other package types. 2. these functions can be multiplexed with other functions. table 8. i/o port latched address output assignments 1 note: 1. refer to the section entitled ai/o portso, on page 39, on how to enable the latched address output function. 2. n/a = not applicable pc5 13 i/o pc5 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. cpld macrocell (mcellbc5) output. 3. input to the plds. 4. tdi input 2 for the jtag interface. this pin can be configured as a cmos or open drain output. pc6 12 i/o pc6 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. cpld macrocell (mcellbc6) output. 3. input to the plds. 4. tdo output 2 for the jtag interface. this pin can be configured as a cmos or open drain output. pc7 11 i/o pc7 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. cpld macrocell (mcellbc7) output. 3. input to the plds. 4. dbe e active-low data byte enable input from 68hc912 type mcus. this pin can be configured as a cmos or open drain output. pd0 10 i/o pd0 pin of port d. this port pin can be configured to have the following functions: 1. ale/as input latches address output from the mcu. 2. mcu i/o e write or read from a standard output or input port. 3. input to the plds. 4. cpld output (external chip select). pd1 9 i/o pd1 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. input to the plds. 3. cpld output (external chip select). 4. clkin e clock input to the cpld macrocells, the automatic power-down unit's power- down counter, and the cpld and array. pd2 8 i/o pd2 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o e write to or read from a standard output or input port. 2. input to the plds. 3. cpld output (external chip select). 4. csi e chip select input. when low, the mcu can access the psd memory and i/o. when high, the psd memory blocks are disabled to conserve power. v cc 15, 38 power pins gnd 1, 16, 26 ground pins microcontroller port a port b port a (3:0) port a (7:4) port b (3:0) port b (7:4) 8051xa (8-bit) n/a address [7:4] address [11:8] n/a 80c251 (page mode) n/a n/a address [11:8] address [15:12] all other 8-bit multiplexed address [3:0] address [7:4] address [3:0] address [7:4] 8-bit non-multiplexed bus n/a n/a address [3:0] address [7:4] pin name pin 1 type description
11/85 m88 family table 9. register address offset note: 1. other registers that are not part of the i/o ports. register name port a port b port c port d other 1 description data in 00 01 10 11 reads port pin as input, mcu i/o input mode control 02 03 selects mode between mcu i/o or address out dataout 04051213 stores data for output to port pins, mcu i/o output mode direction 06 07 14 15 configures port pin as input or output drive select 08 09 16 17 configures port pins as either cmos or open drain on some pins, while selecting high slew rate on other pins. input macrocell 0a 0b 18 reads input macrocells enable out 0c 0d 1a 1b reads the status of the output enable to the i/o port driver output macrocells ab 20 20 read reads output of macrocells ab write loads micro ? cell flip-flops output macrocells bc 21 21 read reads output of macrocells bc write loads micro ? cell flip-flops mask macrocells ab 22 22 blocks writing to the output macrocells ab mask macrocells bc 23 23 blocks writing to the output macrocells bc flash protection c0 read only flash sector protection psd/ee protection c2 read only psd security and eeprom/flash boot sector protection jtag enable c7 enables jtag port pmmr0 b0 power management register 0 pmmr2 b4 power management register 2 page e0 page register vm e2 places psd memory areas in program and/or data space on an individual basis. programmer or to psd simulator for device-level simulation. psdsoft offers direct support for two st device programmers, psdpro, and flashlink (jtag). psdsoft makes available two types of files to support third party programmers. first, the *.obj file is in intel hex format, and is compatible with conventional device programmers. second, the *.svf file is a serial vector format file for jtag-isc device programmers. pin description table 7 describes the pin names and pin functions of the m88x3fxx flash+psd. pins that have multiple names and/or functions are defined using psd configuration. m88x3fxx flash+psd register description and address offset table 9 shows the offset addresses to the m88x3fxx flash+psd registers relative to the csiop base address. the csiop space is the 256 bytes of address that is allocated by the user to the internal m88x3fxx flash+psd registers. table 9 provides brief descriptions of the registers
m88 family 12/85 in csiop space. the following section gives a more detailed description. m88 family functional blocks as shown in figure 3, the m88x3fxx flash+psd consists of six major types of functional blocks: o memory blocks o pld blocks o bus interface o i/o ports o power management unit o jtag interface the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. memory blocks the m88x3fxx flash+psd has the following memory blocks: the main flash memory optional secondary eeprom or flash boot memory optional sram. the memory select signals for these blocks originate from the decode pld (dpld) and are user-defined in psdsoft. table 10 summarizes which versions of the m88x3fxx flash+psd contain which memory blocks. main flash and optional secondary eeprom or flash boot memory description the 1 mbit main flash memory block is divided evenly into eight 16 kbyte sectors. the optional eeprom or flash boot memory is divided into four sectors of 8 kbytes each. each sector of either memory can be separately protected from program and erase operations. flash memory may be erased on a sector-by- sector basis and programmed byte-by-byte. flash sector erasure may be suspended while data is read from other sectors of memory and then resumed after reading. eeprom may be programmed byte-by-byte or sector-by-sector, and erasing is automatic and transparent. the integrity of the data can be secured with the help of software data protection (sdp). any write operation to the eeprom is inhibited during the first five milliseconds following power-up. during a program or erase of flash, or during a write of the eeprom, the status can be output on the ready/busy pin of port c3. this pin is set up using psdsoft configuration. memory block selects the decode pld in the m88x3fxx flash+psd generates the chip selects for all the internal memory blocks (refer to the section entitled adecode pld (dpld)o, on page 25). each of the eight flash memory sectors have a flash select signal (fs0-fs7) which can contain up to three product terms. each of the optional four eeprom or flash boot memory sectors have a select signal (ees0-3 or csboot0-3) which can contain up to three product terms. having three product terms for each sector select signal allows a given sector to be mapped in different areas of system memory. when using a microcontroller with separate program and data space, these flexible select signals allow dynamic re-mapping of sectors from one space to the other. the ready/busy pin (pc3) pin pc3 can be used to output the ready/busy status of the m88x3fxx flash+psd. the output on the pin will be a `0' (busy) when flash or eeprom memory blocks are being written to, or when the flash memory block is being erased. the output will be a `1' (ready) when no write or erase operation is in progress. memory operation the main flash and optional eeprom or flash boot memories are addressed through the microcontroller interface on the m88x3fxx flash+psd device. the microcontroller can access these memories in one of two ways: o the microcontroller can execute a typical bus write or read operation just as it would if accessing a ram or rom device using standard bus cycles. o the microcontroller can execute a specific instruction that consists of several write and read operations. this involves writing specific data patterns to special addresses within the flash or eeprom to invoke an embedded algorithm. these instructions are summarized in table 11. typically, flash memory can be read by the microcontroller using read operations, just as it table 10. memory blocks device 128 kbyte main flash 32 kbyte eeprom 32 kbyte boot flash 2 kbyte sram m8813f1x yes yes no yes m8803f2x yes no yes no m8813f2x yes no yes yes m8803f3x yes no no no m8813f3x yes no no yes
13/85 m88 family would read a rom device. however, flash memory can only be erased and programmed with specific instructions. for example, the microcontroller cannot write a single byte directly to flash memory as one would write a byte to ram. to program a byte into flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event. this status test is achieved by a read operation or polling the ready/busy pin (pc3). the flash memory can also be read by using special instructions to retrieve particular flash device information (sector protect status and id). the eeprom is a bit different. data can be written to eeprom memory using write operations, like writing to a ram device, but the status of each write event must be checked by the microcontroller. a write event can be one to 64 contiguous bytes. the status test is very similar to that used for flash memory (read operation or ready/busy). optionally, the eeprom memory may be put into a software data protect (sdp) mode where it requires instructions, rather than operations, to alter its contents. sdp mode makes writing to eeprom much like writing to flash memory. instructions an instruction is defined as a sequence of specific operations. each received byte is sequentially decoded by the psd and not executed as a standard write operation. the instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. some instructions are structured to include read operations after the initial write operations. the sequencing of any instruction must be followed exactly. any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing flash memory will reset the device logic into a read array mode (flash memory reads like a rom device). an invalid combination or time-out while addressing the eeprom block will cause the offending byte to be interpreted as a single operation. the m88x3fxx flash+psd supports these instructions (see table 11): flash memory: o erase memory by chip or sector o suspend or resume sector erase o program a byte o reset to read array mode o read flash identifier value o read sector protection status optional eeprom: o write data to otp row o read data from otp row o power down memory o enable software data protect (sdp) o disable sdp o return from read otp row read mode or power down mode. these instructions are detailed in table 11. for efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. the coded cycles consist of writing the data aah to address x555h during the first cycle and data 55h to address xaaah during the second cycle. address lines a15-a12 are don't cares during the instruction write cycles. however, the appropriate sector select signal (fsi, eesi, or csbooti) must be selected. power down instruction and power up condition eeprom power down instruction (m8813f1x only) the eeprom can enter power down mode with the help of the eeprom power down instruction (see table 11). once the eeprom power down instruction is decoded, the eeprom memory cannot be accessed unless a return instruction (also in table 11) is decoded. alternately, this power down mode will automatically occur when the apd circuit is triggered (see the section entitled aautomatic power down (apd) unit and power down modeo, on page 48). therefore, this instruction is not required if the apd circuit is used. power-up condition the m88x3fxx flash+psd internal logic is reset upon power-up to the read array mode. any write operation to the eeprom is inhibited during the first 5 ms following power-up. the fsi and eesi/ csbooti select signals, along with the write strobe signal, must be in the false state during power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of a write strobe signal. any write cycle initiation is locked when v cc is below v lko . read under typical conditions, the microcontroller may read the flash, eeprom, or flash boot memories using read operations just as it would a rom or ram device. alternately, the microcontroller may use read operations to obtain status information about a program or erase operation in progress. lastly, the microcontroller may use instructions to read special data from these memories. the following sections describe these read functions.
m88 family 14/85 table 11. instructions note: 1. additional sectors to be erased must be entered within 80 m s. a sector address is any address within the sector. 2. flash and eeprom sector selects are active high. addresses a15-a12 are don't cares in instruction bus cycles. 3. the reset instruction is required to return to the normal read array mode if dq5 goes high, or after reading the flash identifier or the protection status. 4. the mcu cannot invoke these instructions while executing code from eeprom. the mcu must be operating from some other memory when these instructions are performed. 5. the mcu cannot invoke these instructions while executing code from the same flash memory as that for which the instruction is intended. the mcu must be operating from some other memory when these instructions are performed. 6. writing to the otp row is allowed only when the sdp mode is disabled. instruction eeprom sector select (eesi) flash sector select 2 (fsi, csbooti) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read flash identifier 3 0 1 5 aah@ x555h 55h@ xaaah 90h@ x555h read identifier (a6,a1,a0 = 0,0,1) read otp row 1 4 0 aah@ x555h 55h@ xaaah 90h@ x555h read byte 1 read byte 2 read byte n read sector protection status 3 0 1 5 aah@ x555h 55h@ xaaah 90h@ x555h read identifier (a6,a1,a0 = 0,1,0) program a flash byte 0 1 5 aah@ x555h 55h@ xaaah a0h@ x555h data@ address erase one flash sector 0 1 5 aah@ x555h 55h@ xaaah 80h@ x555h aah@ x555h 55h@ xaaah 30h@ sector address 30h 1 @ sector address erase the whole flash 0 1 5 aah@ x555h 55h@ xaaah 80h@ x555h aah@ x555h 55h@ xaaah 10h@ x555h suspend sector erase 0 1 5 b0h@ any address resume sector erase 0 1 5 30h@ any address eeprom power down 1 4 0 aah@ x555h 55h@ xaaah 30h@ x555h sdp enable / eeprom write 1 4 0 aah@ x555h 55h@ xaaah a0h@ x555h write byte 1 write byte 2 write byte n sdp disable 1 4 0 aah@ x555h 55h@ xaaah 80h@ x555h aah@ x555h 55h@ xaaah 20h@ x555h write in otp row 6 1 4 0 aah@ x555h 55h@ xaaah b0h@ x555h write byte 1 write byte 2 write byte n return (from otp read or eeprom power-down) 1 4 0 f0h@ any address reset 3 0 1 5 aah@ x555h 55h@ xaaah f0h@ any address reset (short instruction) 0 1 5 f0h@ any address
15/85 m88 family read the contents of memory main flash and flash boot memories are placed in the read array mode after power-up, chip reset, or a reset flash instruction (see table 11). the microcontroller can read the memory contents of main flash, optional eeprom, or optional flash boot by using read operations any time the read operation is not part of an instruction sequence. read the main flash memory identifier the main flash memory identifier is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see table 11). during the read operation, address bits a6, a1, and a0 must be 0,0,1, respectively, and the appropriate sector select signal (fsi) must be active. see the section entitled aread the main flash memory identifiero, on page 15, for information on how to use the flash memory identifier. read the main flash memory sector protection status the main flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see table 11). during the read operation, address bits a6, a1, and a0 must be 0,1,0, respectively, while the chip select fsi designates the flash sector whose protection has to be verified. the read operation will produce 01h if the flash sector is protected, or 00h if the sector is not protected. the sector protection status for all nvm blocks (main flash, eeprom, or boot flash) can be read by the microcontroller accessing the flash protection and psd/ee protection registers in psd i/o space. see the section entitled aflash and eeprom sector protecto, on page 20, for register definitions. read the otp row (m8813f1x only) there are 64 bytes of one-time-programmable (otp) memory that reside in eeprom. these 64 bytes are in addition to the 32 kbytes of eeprom memory. a read of the otp row is done with an instruction composed of at least 4 operations: 3 specific write operations and one to 64 read operations (see table 11). during the read operation(s), address bit a6 must be zero, while address bits a5-a0 define the otp row byte to be read while any eeprom sector select signal (eesi) is active. after reading the last byte, an eeprom return instruction must be executed (see table 11). read the erase/program status bits the m88x3fxx flash+psd provides several status bits to be used by the microcontroller to confirm the completion of an erase or programming instruction of flash memory. bits are also available to show the status of writes to eeprom. these status bits minimize the time that the microcontroller spends performing these tasks and are defined in table 12. the status bits can be read as many times as needed. for flash memory, the microcontroller can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. see the section entitled aprogramming flash memoryo, on page 18, for details. for eeprom not in sdp mode, the microcontroller can perform a read operation to obtain these status bits just after a data write operation. the microcontroller may write one to 64 bytes before reading the status bits. see the section entitled awriting to the optional eeprom (m8813f1x only)o, on page 16. for eeprom in sdp mode, the microcontroller will perform a read operation to obtain these status bits while an sdp write instruction is being executed by the embedded algorithm. see the section entitled ainstructionso, on page 13, for details. data polling flag dq7 when erasing or programming the flash memory (or when writing into the eeprom memory), bit dq7 outputs the complement of the bit being entered for programming/writing on dq7. once the program instruction or the write operation is completed, the true logic value is read on dq7 (in table 12. status bit note: 1. x = not guaranteed value, can be read either 1 or 0. 2. dq7-dq0 represent the data bus bits, d7-d0. 3. fsi/csbo oti and eesi are active high. fsi/csbooti eesi dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 flash v ih v il data polling toggle flag error flag x erase time- out xxx eeprom v il v ih data polling toggle flag xxxxxx
m88 family 16/85 a read operation). flash memory specific features: o data polling is effective after the fourth write pulse (for programming) or after the sixth write pulse (for erase). it must be performed at the address being programmed or at an address within the flash sector being erased. o during an erase instruction, dq7 outputs a `0'. after completion of the instruction, dq7 will output the last bit programmed (it is a `1' after erasing). o if the byte to be programmed is in a protected flash sector, the instruction is ignored. o if all the flash sectors to be erased are protected, dq7 will be set to `0' for about 100 m s, and then return to the previous addressed byte. no erasure will be performed. toggl e flag dq6 the m88x3fxx flash+psd offers another way for determining when the eeprom write or the flash memory program instruction is completed. during the internal write operation and when either the fsi or eesi/csbooti is true, the dq6 will toggle from `0' to `1' and `1' to `0' on subsequent attempts to read any byte of the memory. when the internal cycle is complete, the toggling will stop and the data read on the data bus d0-7 is the addressed memory byte. the device is now accessible for a new read or write operation. the operation is finished when two successive reads yield the same output data. flash memory specific features: o the toggle bit is effective after the fourth write pulse (for programming) or after the sixth write pulse (for erase). o if the byte to be programmed belongs to a protected flash sector, the instruction is ignored. o if all the flash sectors selected for erasure are protected, dq6 will toggle to `0' for about 100 m s and then return to the previous addressed byte. error flag dq5 during a correct program or erase, the error bit will set to `0'. this bit is set to `1' when there is a failure during flash byte programming, sector erase, or bulk erase. in the case of flash programming, the error bit indicates the attempt to program a flash bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation. the error bit may also indicate a time-out condition while attempting to program a byte. in case of an error in flash sector erase or byte program, the flash sector in which the error occurred or to which the programmed byte belongs must no longer be used. other flash sectors may still be used. the error bit resets after the reset instruction. erase time-out flag dq3 (flash memory only) the erase timer bit reflects the time-out period allowed between two consecutive sector erase instructions. the erase timer bit is set to `0' after a sector erase instruction for a time period of 100 m s + 20% unless an additional sector erase instruction is decoded. after this time period or when the additional sector erase instruction is decoded, dq3 is set to `1'. writing to the optional eeprom (m8813f1x only) data may be written a byte at a time to the eeprom using simple write operations, much like writing to an sram. unlike sram though, the completion of each byte write must be checked before the next byte is written. to speed up this process, the m88x3fxx flash+psd offers a page write feature to allow writing of several bytes before checking status. to prevent inadvertent writes to eeprom, the m88x3fxx flash+psd offers a software data protect (sdp) mode. once enabled, sdp forces the mcu to aunlocko the eeprom before altering its contents, much like flash memory programming. write a byte to eeprom a write operation is initiated when an eeprom select signal (eesi) is true and the write strobe signal (wr) into the m88x3fxx flash+psd is true. if the m88 family detects no additional writes within 200 m s, an internal storage operation is initiated. internal storage to eeprom memory technology typically takes a few milliseconds to complete. the status of the write operation is obtained by the mcu reading the data polling or toggle bits (as detailed in the section entitled areado, on page 13), or the ready/busy output pin (the section entitled athe ready/busy pin (pc3)o, on page 12). keep in mind that the mcu does not need to erase a location in eeprom before writing it. erasure is performed automatically as an internal process. write a page to eeprom (m8813f1x only) writing data to eeprom using page mode is more efficient than writing one byte at a time. the m88x3fxx flash+psd eeprom has a 64 byte volatile buffer that the mcu may fill before an internal eeprom storage operation is initiated. page mode timing approaches a 64:1 advantage over the time it takes to write individual bytes. to invoke page mode, the mcu must write to eeprom locations within a single page, with no more than 200 m s between individual byte writes. a single page means that address lines a14 to a6
17/85 m88 family must remain constant. the mcu may write to the 64 locations on a page in any order, which is determined by address lines a5 to a0. as soon as 200 m s have expired after the last page write, the internal eeprom storage process begins and the mcu checks programming status. status is checked the same way it is for byte writes, described above. it should be noted that if the upper address bits (a14 to a6) change during page write operations, loss of data may occur. ensure that all bytes for a given page have been successfully stored in the eeprom before proceeding to the next page. correct management of mcu interrupts during eeprom page write operations is essential. eeprom software data protect (sdp) the sdp feature is useful for protecting the contents of eeprom from inadvertent write cycles that may occur during uncontrolled mcu bus conditions. these may happen if the application software gets lost or when v cc is not within normal operating range. instructions from the mcu are used to enable and disable sdp mode (see table 11). once enabled, the mcu must write an instruction sequence to eeprom before writing data (much like writing to flash memory). sdp mode can be used for both byte and page writes to eeprom. the device will remain in sdp mode until the mcu issues a valid sdp disable instruction. m88x3fxx flash+psd devices are shipped with sdp mode disabled. however, within psdsoft, sdp mode may be enabled as part of programming the device with a device programmer (psdpro). to enable sdp mode at run time, the mcu must write three specific data bytes at three specific memory locations, as shown in figure 5. any further writes to eeprom when sdp is set will require this same sequence, followed by the byte(s) to write. the first sdp enable sequence can be followed directly by the byte(s) to be written. to disable sdp mode, the mcu must write specific bytes to six specific locations, as shown in figure 6. the mcu must not be executing code from eeprom when these instructions are invoked. the mcu must be operating from some other memory when enabling or disabling sdp mode. the state of sdp mode is not changed by power on/off sequences (nonvolatile). when either the sdp enable or sdp disable instructions are issued from the mcu, the mcu must use the toggle bit (status bit dq6) or the ready/busy output pin to check programming status. the ready/busy output is driven low from the first write of aah @ 555h until the completion of the internal storage sequence. data polling (status bit dq7) is figure 5. eeprom sdp-enable flowcharts ai01698c write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h sdp is set write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h write data to be written in any address sdp enable algorithm page write timing page write timing write is enabled sdp set sdp not set write in memory write data and sdp set after t wc
m88 family 18/85 figure 6. eeprom sdp-disable flowchart ai01699c write aah in address 5555h write 55h in address 2aaah write 80h in address 5555h unprotected state after t wc (write cycle time) write aah in address 5555h write 55h in address 2aaah write 20h in address 5555h page write timing not supported when issuing the sdp enable or sdp disable commands. using the sdp sequence (enabling, disabling, or writing data) is initiated when specific bytes are written to addresses on specific apageso of eeprom memory, with no more than 120 m s between writes. the addresses 555h and aaah are located on different pages of eeprom. this is how the m88x3fxx flash+psd distinguishes these instruction sequences from ordinary writes to eeprom, which are expected to be within a single eeprom page. write otp row (m8813f1x only) writing to the otp row (64 bytes) can only be done once, and is enabled by an instruction. this instruction is composed of three specific write operations of data bytes at three specific memory locations followed by the data to be stored in the otp row (refer to table 11). during the write operations, address bit a6 must be zero, while address bits a5-a0 define the otp row byte to be written while any eeprom sector select signal (eesi) is active. writing the otp row is allowed only when the sdp mode is not enabled. programming flash memory flash memory must be erased prior to being programmed. the mcu may erase flash memory all at once or by-sector, but not byte-by-byte. a byte of flash memory erases to all logic ones (ff hex), and its bits are programmed to logic zeros. although erasing flash memory occurs on a sector basis, programming flash memory occurs on a byte basis. the m88x3fxx flash+psd main flash and optional boot flash require the mcu to send an instruction to program a byte or perform an erase function (see table 11). this differs from eeprom, which can be programmed with simple mcu bus write operations (unless eeprom sdp mode is enabled). once the mcu issues a flash memory program or erase instruction, it must check for the status of completion. the embedded algorithms that are invoked inside the m88x3fxx flash+psd support several means to provide status to the mcu. status may be checked using any of three methods: data polling, data toggle, or the ready/ busy output pin. data polling polling on dq7 is a method of checking whether a program or erase instruction is in progress or has completed. figure 7 shows the data polling algorithm. when the mcu issues a programming instruction, the embedded algorithm within the m88x3fxx flash+psd begins. the mcu then reads the location of the byte to be programmed in flash to check status. data bit dq7 of this location becomes the compliment of data bit 7of the original data byte to be programmed. the mcu continues to poll this location, comparing dq7 and monitoring the error bit on dq5. when the dq7 matches data bit 7 of the original data, and the error bit at dq5 remains `0', then the embedded algorithm is complete. if the error bit at dq5 is `1', the mcu should test dq7 again since dq7 may have changed simultaneously with dq5 (see figure 7). the error bit at dq5 will be set if either an internal time-out occurred while the embedded algorithm attempted to program the byte or if the mcu attempted to program a `1' to a bit that was not erased (not erased is logic `0'). it is suggested (as with all flash memories) to read the location again after the embedded programming algorithm has completed to compare the byte that was written to flash with the byte that was intended to be written. when using the data polling method after an erase instruction, figure 7 still applies. however, dq7 will be `0' until the erase operation is complete. a `1' on dq5 will indicate a time-out failure of the erase operation, a `0' indicates no error. the mcu can read any location within the sector being erased to get dq7 and dq5.
19/85 m88 family figure 8. data toggl e flowchart read dq5 & dq6 start read dq6 fail pass ai01370b dq6 = toggle no no yes yes dq5 =1 no yes dq6 = toggle figure 7. data polling flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai01369b dq7 = data yes no yes no dq5 =1 dq7 = data yes no psdsoft will generate ansi c code functions which implement these data polling algorithms. data toggle checking the data toggle bit on dq6 is a method of determining whether a program or erase instruction is in progress or has completed. figure 8 shows the data toggle algorithm. when the mcu issues a programming instruction, the embedded algorithm within the m88x3fxx flash+psd begins. the mcu then reads the location of the byte to be programmed in flash to check status. data bit dq6 of this location will toggle each time the mcu reads this location until the embedded algorithm is complete. the mcu continues to read this location, checking dq6 and monitoring the error bit on dq5. when dq6 stops toggling (two consecutive reads yield the same value), and the error bit on dq5 remains `0', then the embedded algorithm is complete. if the error bit on dq5 is `1', the mcu should test dq6 again, since dq6 may have changed simultaneously with dq5 (see figure 8). the error bit at dq5 will be set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the mcu attempted to program a `1' to a bit that was not erased (not erased is logic `0'). it is suggested (as with all flash memories) to read the location again after the embedded programming algorithm has completed to compare the byte that was written to flash with the byte that was intended to be written. when using the data toggle method after an erase instruction, figure 8 still applies. dq6 will toggle until the erase operation is complete. a `1' on dq5 will indicate a time-out failure of the erase operation, a `0' indicates no error. the mcu can read any location within the sector being erased to get dq6 and dq5. psdsoft will generate ansi c code functions which implement these data toggling algorithms. erasing flash memory flash bulk erase instruction the flash bulk erase instruction uses six write operations followed by a read operation of the status register, as described in table 11. if any byte of the bulk erase instruction is wrong, the bulk erase instruction aborts and the device is reset to the read flash memory status. during a bulk erase, the memory status may be checked by reading status bits dq5, dq6, and dq7, as detailed in the section entitled aprogramming flash memoryo, on page 18. the
m88 family 20/85 error bit (dq5) returns a `1' if there has been an erase failure (maximum number of erase cycles have been executed). it is not necessary to program the array with 00h because the m88x3fxx flash+psd will automatically do this before erasing to 0ffh. during execution of the bulk erase instruction, the flash memory will not accept any instructions. flash sector erase instruction the sector erase instruction uses six write operations, as described in table 11. additional flash sector erase confirm commands and flash sector addresses can be written subsequently to erase other flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the time-out period of about 100 m s. the input of a new sector erase instruction will restart the time-out period. the status of the internal timer can be monitored through the level of dq3 (erase time-out bit). if dq3 is `0', the sector erase instruction has been received and the time-out is counting. if dq3 is `1', the time-out has expired and the m88x3fxx flash+psd is busy erasing the flash sector(s). before and during erase time-out, any instruction other than erase suspend and erase resume will abort the instruction and reset the device to read array mode. it is not necessary to program the flash sector with 00h as the m8813f1x will do this automatically before erasing (byte=ffh). during a sector erase, the memory status may be checked by reading status bits dq5, dq6, and dq7, as detailed in the section entitled aprogramming flash memoryo, on page 18. during execution of the erase instruction, the flash block logic accepts only reset and erase suspend instructions. erasure of one flash sector may be suspended, in order to read data from another flash sector, and then resumed. flash erase suspend instruction when a flash sector erase operation is in progress, the erase suspend instruction will suspend the operation by writing 0b0h to any address when an appropriate chip select (fsi or csbooti) is true. (see table 11). this allows reading of data from another flash sector after the erase operation has been suspended. erase suspend is accepted only during the flash sector erase instruction execution and defaults to read array mode. an erase suspend instruction executed during an erase time-out will, in addition to suspending the erase, terminate the time out. the toggle bit dq6 stops toggling when the m88x3fxx flash+psd internal logic is suspended. the toggle bit status must be monitored at an address within the flash sector being erased. the toggle bit will stop toggling between 0.1 m s and 15 m s after the erase suspend instruction has been executed. the m88x3fxx flash+psd will then automatically be set to read flash block memory array mode. if an erase suspend instruction was executed, the following rules apply: attempting to read from a flash sector that was being erased will output invalid data. reading from a flash sector that was not being erased is valid. the flash memory cannot be programmed, and will only respond to erase resume and reset instructions (read is an operation and is ok). if a reset instruction is received, data in the flash sector that was being erased will be invalid. flash erase resume instruction if an erase suspend instruction was previously executed, the erase operation may be resumed by this instruction. the erase resume instruction consists of writing 030h to any address while an appropriate chip select (fsi or csbooti) is true. (see table 11.) flash and eeprom memory specific features flash and eeprom sector protect each flash and eeprom sector can be separately protected against program and erase functions. sector protection provides additional data security because it disables all program or erase operations. this mode can be activated through the jtag port or a device programmer. sector protection can be selected for each sector using the psdsoft configuration program. this will automatically protect selected sectors when the device is programmed through the jtag port or a device programmer. flash and table 13. sector protection/security bit definitio n flash protection register note: 1. bit definitions: sec_prot 1 = flash or flash boot sector is write protected. sec_prot 0 = flash or flash boot sector is not write protected. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot
21/85 m88 family table 14. sector protection/security bit definition psd/ee protection register note: 1. bit definitions: sec_prot 1 = eeprom or flash boot sector is write protected. sec_prot 0 = eeprom or flash boot sector is not write protected. security_bit 0 = security bit in device has not been set. 1 = security bit in device has been set. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 security_bit not used not used not used sec3_prot sec2_prot sec1_prot sec0_prot eeprom sectors can be unprotected to allow updating of their contents using the jtag port or a device programmer. the microcontroller can read (but cannot change) the sector protection bits. any attempt to program or erase a protected flash or eeprom sector will be ignored by the device. the verify operation will result in a read of the protected data. this allows a guarantee of the retention of the protection status. the sector protection status can be read by the mcu through the flash protection and psd/ee protection registers (csiop). see table 13 and table 14. reset instruction the reset instruction resets the internal memory logic state machine in a few milliseconds. reset is an instruction of either one write operation or three write operations (refer to table 11). sram the sram is a 16 kbit (2k x 8) memory. the sram is enabled when rs0ethe sram chip select output from the dpldeis high. rs0 can contain up to two product terms, allowing flexible memory mapping. the sram can be backed up using an external battery. the external battery should be connected to the vstby pin (pc2). if you have an external battery connected to the m8813fxx flash+psd, the contents of the sram will be retained in the event of a power loss. the contents of the sram will be retained so long as the battery voltage remains at 2v or greater. if the supply voltage falls below the battery voltage, an internal power switch-over to the battery occurs. pin pc4 can be configured as an output that indicates when power is being drawn from the external battery. this v baton signal will be high with the supply voltage falls below the battery voltage and the battery on pc2 is supplying power to the internal sram. the chip select signal (rs0) for the sram, v stby , and v baton are all configured using psdsoft configuration. memory select signals the main flash (fsi), optional eeprom or flash boot (eesi/csbooti), and sram (rs0) memory select signals are all outputs of the dpld. they are setup by writing equations for them in psdabel. the following rules apply to the equations for the internal chip select signals: 1. flash memory and eeprom or flash boot memory sector select signals must not be larger than the physical sector size. 2. any main flash memory sector must not be mapped in the same memory space as another flash sector. 3. an eeprom/flash boot memory sector must not be mapped in the same memory space as another eeprom/flash boot sector. 4. sram, i/o, and peripheral i/o spaces must not overlap. 5. an eeprom/flash boot memory sector may overlap a main flash memory sector. in case of overlap, priority will be given to the eeprom/ flash boot sector. 6. sram, i/o, and peripheral i/o spaces may overlap any other memory sector. priority will be given to the sram, i/o, or peripheral i/o. example fs0 is valid when the address is in the range of 8000h to bfffh, ees0 is valid from 8000h to 9fffh, and rs0 is valid from 8000h to 87ffh. any address in the range of rs0 will always access the sram. any address in the range of ees0 greater than 87ffh (and less than 9fffh) will automatically address eeprom memory segment 0. any address greater than 9fffh will access the flash memory segment 0. you can see that half of the flash memory segment 0 and one- fourth of eeprom segment 0 can not be accessed in this example. also note that an equation that defined fs1 to anywhere in the range of 8000h to bfffh would not be valid. figure 9 shows the priority levels for all memory components. any component on a higher level can overlap and has priority over any component on a lower level. components on the same level must not overlap. level one has the highest priority and level 3 has the lowest.
m88 family 22/85 memory select configur ation for mcus with separate program and data spaces the 8031 and compatible family of microcontrollers, which includes the 80c51, 80c151, 80c251, and 80c51xa, have separate address spaces for code memory (selected using psen) and data memory (selected using rd). any of the memories within the m88x3fxx flash+psd can reside in either space or both spaces. this is controlled through manipulation of the vm register that resides in the psd's csiop space. the vm register is set using psdsoft to have an initial value. it can subsequently be changed by the microcontroller so that memory mapping can be changed on-the-fly. for example, i may wish to have sram and flash in data space at boot, and eeprom in program space at boot, and later swap eeprom and flash. this is easily done with the vm register by using psdsoft configuration to configure it for boot up and having the microcontroller change it when desired. table 15 describes the vm register. configurati on modes for mcus with separate program and data spaces separate space modes code memory space is separated from data memory space. for example, the psen signal is used to access the program code from the flash memory, while the rd signal is used to access data from the eeprom, sram and i/o ports. this configuration requires the vm register to be set to 0ch. combined space modes the program and data memory spaces are combined into one space that allows the main flash memory, eeprom, and sram to be accessed by either psen or rd. for example, to configure the main flash memory in combined space mode, bits 2 and 4 of the vm register are set to a1o. mixed modes this allows individual flash memory or eeprom sectors with overlapping addresses to be configured in either data space or program space. flash memory or eeprom sector select signals must be qualified with the rd input in the fs0-fs7 or ees0-ees3 equations. an active rd will select memory sectors in the data space and disable the sectors that are in the program space. for memory sectors that reside in data space, the access time is calculated from rd valid to data valid. this mode is set automatically by psdsoft whenever the rd signal is included in the memory sector chip select equations. 80c31 memory map example in this example, the psd memory will be configured as shown in figure 10. o flash memory sectors fs0-1 will be mapped from 8000h-ffffh in the combined space mode (in both program space and data space). bits 2 and 4 of the vm register are set to 1. table 15. vm register bit 7 pio_en bit 6 bit 5 bit 4 fl_data bit 3 ee_data bit 2 fl_code bit 1 ee_code bit 0 sram_code 0 = disable pio mode not used not used 0=rd can't access flash 0=rd can't access eeprom/ boot flash 0 = psen can't access flash 0 = psen can't access eeprom/ boot flash 0 = psen can't access sram 1= enable pio mode not used not used 1=rd access flash 1=rd access eeprom/ boot flash 1 = psen access flash 1 = psen access eeprom/ boot flash 1 = psen access sram figure 9. priori ty level of memory and i/o components level 1 sram, i/o, or peripheral i/o level 2 eeprom/ flash boot memory highest priority lowest priority level 3 flash memory ai02867
23/85 m88 family o eeprom sectors ees0-1 will be mapped in the program space from 0000h-3fffh. eeprom sectors ees2-3 will be mapped in the data space from 0000h-3fffh. bits 1 and 3 of the vm register are set to 1. o sram will be mapped in the data space from 4000h-47ffh. bit 0 of the vm register is set to 0. the abel equations in psdsoft will be as followed (assumes active-low rd signal): fs0 = (address>= ^h8000) & (address<=^hbfff ); fs1 = (address>= ^hc000) & (address<=^hffff ); ees0 = (address>= ^h0000) & (address<=^h1fff ) & rd; ees1 = (address>= ^h2000) & (address<=^h3fff ) & rd; ees2 = (address>= ^h0000) & (address<=^h1fff ) & !rd; ees3 = (address>= ^h2000) & (address<=^h3fff ) & !rd; rs0 = (address>= ^h4000) & (address<=^h47ff); when the microcontroller reads the vm register, the contents read back are shown in table 16. the vm register content at power up is specified in psdsoft. page register the eight bit page register increases the addressing capability of the microcontroller by a factor of up to 256. the contents of the register can also be read by the microcontroller. the outputs of the page register (pgr0-pgr7) are inputs to the dpld decoder and can be included in the flash memory, eeprom, and sram chip select equations. if memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the cpld for general logic. see application note an1154. figure 13 shows the page register. the eight flip flops in the register are connected to the internal data bus d0-d7. the microcontroller can write to or read from the page register. the page register can be accessed at address location csiop + e0h. plds the plds bring programmable logic functionality to the m88x3fxx flash+psd. after specifying the logic for the plds using the psdabel tool in psdsoft, the logic is programmed into the device and available upon power-up. the m88x3fxx flash+psd contains two plds: the decode pld (dpld), and the complex pld (cpld). the plds are briefly discussed in the next few paragraphs, and in more detail in the section entitled adecode pld (dpld)o, on page 25, and the section entitled acomplex pld (cpld)o, also on page 25. figure 14 shows the configuration of the plds. the dpld performs address decoding for internal and external components, such as memory, registers, and i/o port selects. the cpld can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. these logic functions can be constructed using the 16 output macrocells (omcs), 24 input macrocells (imcs), and the and array. the cpld can also be used to generate external chip selects. the and array is used to form product terms. these product terms are specified using psdabel. an input bus consisting of 73 signals is connected to the plds. the signals are shown in table 17. the turbo bit in m88x3fxx flash+psd the plds in the m88 family can minimize power consumption by switching off when inputs remain table 16. vm register contents in the 80c31 memory map example bit 7 pio_en bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 rd_en bit 0 psen_en 0 = disable pio mode not used not used 1=rd can access flash 1=rd can access eeprom/ boot flash 1 = psen can access flash 1 = psen can access eeprom/ boot flash 0 = psen cannot access sram figure 10. 80c31 memory map example flash memory sectors fs0-1 program space eeprom sectors ees0-1 ffffh 8000h 4000h 0 flash memory sectors fs0-1 data space sram eeprom sectors ees2-3 ffffh 8000h 47ffh 4000h 0 ai02868
m88 family 24/85 figure 11. 8031 memory modules separate space mode figure 12. 8031 memory modules combined space mode flash dpld eeprom sram rs0 ees0-3 fs0-7 cs cs cs oe oe rd psen oe ai02869 flash dpld eeprom sram rs0 ees0-3 fs0-7 rd cs cs cs rd oe oe vm reg bit 2 psen vm reg bit 0 vm reg bit 1 vm reg bit 3 vm reg bit 4 oe ai02870 unchanged for an extended time of about 70 ns. setting the turbo mode bit to off (bit 3 of the pmmr0 register) automatically places the plds into standby if no inputs are changing. turbo-off mode increases propagation delays while reducing power consumption. refer to the section entitled apower management unito, on page 7, on how to set the turbo bit. additionally, five bits are available in the pmmr2 register to block mcu control signals from entering the plds. this reduces power consumption and can be used only when these mcu control signals are not used in pld logic equations. each of the two plds has unique characteristics suited for its applications they are described in the following sections.
25/85 m88 family figure 13. page register reset d0 - d7 r/w d0 q0 q1 q2 q3 q4 q5 q6 q7 d1 d2 d3 d4 d5 d6 d7 page register pgr0 pgr1 pgr2 pgr3 flash dpld and flash cpld internal selects and logic flash pld pgr4 pgr5 pgr6 pgr7 ai02871 decode pld (dpld) the dpld, shown in figure 15, is used for decoding the address for internal and external components. the dpld can generate the following decode signals: n 8 sector selects for the main flash memory (three product terms each) n 4 sector selects for the optional eeprom or flash boot memory (three product terms each) n 1 internal sram select signal (two product terms) n 1 internal csiop (psd configuration register) select signal n 1 jtag select signal (enables jtag on port c) n 2 internal peripheral select signals (peripheral i/o mode). complex pld (cpld) the cpld can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. the cpld can also be used to generate 3 external chip selects, routed to port d. although external chip selects can be produced by any output macrocell, these three external chip selects on port d do not consume any output macrocells. as shown in figure 14, the cpld has the following blocks: n 24 input macrocells (imcs) n 16 output macrocells (omcs) n macrocell allocator n product term allocator n and array capable of generating up to 140 product terms n four i/o ports. table 17. dpld and cpld inputs note: 1. the address inputs are a[19:4] in 80c51xa mode. input source input name number of signals mcu address bus 1 a[15:0] 16 mcu control signals cntl[2:0] 3 reset rst 1 power down pdn 1 port a input macrocells pa[7-0] 8 port b input macrocells pb[7-0] 8 port c input macrocells pc[7-0] 8 port d inputs pd[2:0] 3 page register pgr(7:0) 8 macrocell ab feedback mcellab.fb[7:0] 8 macrocell bc feedback mcellbc.fb[7:0] 8 eeprom/boot flash programming status bit ready/busy 1
m88 family 26/85 figure 14. pld block diagram pld input bus 8 input macrocell & input ports direct macrocell input to mcu data bus csiop select sram select flash eeprom selects (m8813f1x) or flash boot memory selects (m8813f2x) decode pld page register peripheral selects jtag select cpld pt alloc. macrocell alloc. mcellab mcellbc direct macrocell access from mcu data bus 24 input macrocell (port a,b,c) 16 output macrocell i/o ports flash memory selects 3 port d inputs to port a or b to port b or c data bus 8 8 8 4 1 1 2 1 external chip selects to port d 3 73 16 73 24 output macrocell feedback ai02872
27/85 m88 family figure 15. dpld logic array (inputs) (24) (8) (16) (1) pdn (apd output) i/o ports (port a,b,c) (8) pgr0 -pgr7 (8) mcellab.fb [7:0] (feedbacks) mcellbc.fb [7:0] (feedbacks) a [ 15:0 ] * (3) (3) pd [ 2:0 ] (ale,clkin,csi) cntrl [ 2:0 ]( read/write control signals) (1) (1) reset rd_bsy rs0 csiop psel0 psel1 8 flash memory sector selects sram select i/o decoder select peripheral i/o mode select ees0 or csboot 0 ees1 or csboot 1 ees2 or csboot 2 ees3 or csboot 3 fs0 fs7 3 3 3 3 3 3 3 3 3 3 3 3 2 jtagsel ai02873 * the address inputs are a [ 19:4] in 80c51xa mode fs1 fs2 fs3 fs6 fs5 fs4
m88 family 28/85 figure 16. the macrocell and i/o port i/o ports cpld macrocells input macrocells latched address out mux mux mux mux mux d d q q q g d qd wr wr pdr data product term allocator dir reg. select input product terms from other macrocells polarity select up to 10 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable ( oe ) macrocell feedback i/o port input ale/as pt input latch gate/clock mcu load pt preset mcu data in comb. /reg select macrocell to i/o port alloc. cpld output to other i/o ports pld input bus pld input bus mcu address / data bus macrocell out to mcu data load control and array cpld output i/o pin ai02874
29/85 m88 family table 18. output macrocell port and data bit assignments output macrocell port assignment native product terms maximum borrowed product terms data bit for loading or reading mcellab0 port a0, b0 3 6 d0 mcellab1 port a1, b1 3 6 d1 mcellab2 port a2, b2 3 6 d2 mcellab3 port a3, b3 3 6 d3 mcellab4 port a4, b4 3 6 d4 mcellab5 port a5, b5 3 6 d5 mcellab6 port a6, b6 3 6 d6 mcellab7 port a7, b7 3 6 d7 mcellbc0 port b0, c0 4 5 d0 mcellbc1 port b1, c1 4 5 d1 mcellbc2 port b2, c2 4 5 d2 mcellbc3 port b3, c3 4 5 d3 mcellbc4 port b4, c4 4 6 d4 mcellbc5 port b5, c5 4 6 d5 mcellbc6 port b6, c6 4 6 d6 mcellbc7 port b7, c7 4 6 d7 each of the blocks are described in the sections that follow. the input and output macrocells are connected to the m88x3fxx flash+psd internal data bus and can be directly accessed by the microcontroller. this enables the mcu software to load data into the output macrocells or read data from both the input and output macrocells. this feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the and logic array as required in most standard pld macrocell architectures. output macrocell eight of the output macrocells are connected to ports a and b pins and are named as mcellab0-7. the other eight macrocells are connected to ports b and c pins and are named as mcellbc0-7. if an mcellab output is not assigned to a specific pin in psdabel, the macrocell allocator will assign it to either port a or b. the same is true for a mcellbc output on port b or c. table 18 shows the macrocells and port assignment. the output macrocell (omc) architecture is shown in figure 17. as shown in the figure, there are native product terms available from the and array, and borrowed product terms available (if unused) from other omcs. the polarity of the product term is controlled by the xor gate. the omc can implement either sequential logic, using the flip-flop element, or combinatorial logic. the multiplexer selects between the sequential or combinatorial logic outputs. the multiplexer output can drive a port pin and has a feedback path to the and array inputs. the flip-flop in the omc can be configured as a d, t, jk, or sr type in the psdabel program. the flip-flop's clock, preset, and clear inputs may be driven from a product term of the and array. alternatively, the external clkin signal can be used for the clock input to the flip-flop. the flip-flop is clocked on the rising edge of the clock input. the preset and clear are active-high inputs. each clear input can use up to two product terms. the product term allocator the cpld has a product term allocator. the psdabel compiler, in psdsoft, uses the allocator to borrow and place product terms from one macrocell to another. the following list summarizes how product terms are allocated: n mcellab0-7 all have three native product terms and may borrow up to six more n mcellbc0-3 all have four native product terms and may borrow up to five more
m88 family 30/85 figure 17. cpld output macrocell pt allocator mask reg. pt clk pt pt pt clkin feedback ( .fb ) port input and array pld input bus mux mux polarity select ld in clr q pr din comb/reg select port driver input macrocell i/o pin macrocell allocator internal data bus d [ 7:0 ] direction register clear ( .re ) programmable ff ( d/t/jk/sr ) wr enable (.oe) preset(.pr) rd macrocell cs ai02875
31/85 m88 family figure 18. input macrocell output macrocells bc and macrocell ab pt pt feedback and array pld input bus port driver i/o pin internal data bus d [ 7:0 ] direction register mux mux ale/as pt q q d d g latch input macrocell enable ( .oe ) dff input macrocell _ rd ai02876 n mcellbc4-7 all have four native product terms and may borrow up to six more. each macrocell may only borrow product terms from certain other macrocells. product terms already in use by one macrocell will not be available for a different macrocell. if an equation requires more product terms than what is available to it, then aexternalo product terms will be required, which will consume other omcs. if external product terms are used, extra delay will be added for the equation that required the extra product terms. this is called product term expansion. psdsoft will perform this expansion as needed. loading and reading the output macrocells (omcs) the omcs occupy a memory location in the mcu address space, as defined by the csiop (refer to
m88 family 32/85 figure 19. handshaking communication using input macrocells master mcu mcu-rd mcu-rd mcu-wr slavewr slavecs mcu-wr d [ 7:0 ] d [ 7:0 ] cpld dq qd port a data out register port a input macrocell port a slaveread slave mcu rd wr m88x3fx ai02877
33/85 m88 family the section entitled ai/o portso, on page 39). the flip-flops in each of the 16 omcs can be loaded from the data bus by a microcontroller. loading the omcs with data from the mcu takes priority over internal functions. as such, the preset, clear, and clock inputs to the flip-flop can be overridden by the mcu. the ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. data can be loaded to the omcs on the trailing edge of the wr signal (edge loading) or during the time that the wr signal is active (level loading). the method of loading is specified in psdsoft configuration. the omc mask register there is one mask register for each of the two groups of eight omcs. the mask registers can be used to block the loading of data to individual omcs. the default value for the mask registers is 00h, which allows loading of the omcs. when a given bit in a mask register is set to a `1', the mcu will be blocked from writing to the associated omc. for example, suppose mcellab0-3 are being used for a state machine. you would not want a mcu write to mcellab to overwrite the state machine registers. therefore, you would want to load the mask register for mcellab (mask macrocell ab) with the value 0fh. the output enable of the omc the omc can be connected to an i/o port pin as a pld output. the output enable of each port pin driver is controlled by a single product term from the and array, ored with the direction register output. the pin is enabled upon power up if no output enable equation is defined and if the pin is declared as a pld output in psdsoft. if the omc output is declared as an internal node and not as a port pin output in the psdabel file, then the port pin can be used for other i/o functions. the internal node feedback can be routed as an input to the and array. input macrocells (imcs) the cpld has 24 imcs, one for each pin on ports a, b, and c. the architecture of the imc is shown in figure 18. the imcs are individually configurable, and can be used as a latch, register, table 19. microcontrollers and their control signals note: 1. unused cntl2 pin can be configured as cpld input. other unused pins (pc7, pd0, pa3-0) can be configured for other i/o func- tions. 2. ale/as input is optional for microcontrollers with a non-multiplexed bus mcu data bus width cntl0 cntl1 cntl2 pc7 pd0 2 adio0 pa3-pa0 pa7-pa3 8031 8 wr rd psen (note 1 ) ale a0 (note 1 ) (note 1 ) 80c51xa 8 wr rd psen (note 1 ) ale a4 a3-a0 (note 1 ) 80c251 8 wr psen (note 1 ) (note 1 ) ale a0 (note 1 ) (note 1 ) 80c251 8 wr rd psen (note 1 ) ale a0 (note 1 ) (note 1 ) 80198 8 wr rd (note 1 ) (note 1 ) ale a0 (note 1 ) (note 1 ) 68hc11 8 r/w e (note 1 ) (note 1 ) as a0 (note 1 ) (note 1 ) 68hc912 8 r/w e (note 1 ) dbe as a0 (note 1 ) (note 1 ) z80 8 wr rd (note 1 ) (note 1 ) (note 1 ) a0 d3-d0 d7-d4 neuron 3150 chip 8 r/w e (note 1 ) (note 1 ) (note 1 ) a0 d3-d0 d7-d4 z8 8 r/w ds (note 1 ) (note 1 ) as a0 (note 1 ) (note 1 ) 68330 8 r/w ds (note 1 ) (note 1 ) as a0 (note 1 ) (note 1 ) m37702m2 8 r/w e (note 1 ) (note 1 ) ale a0 d3-d0 d7-d4 table 20. eight-bit data bus bhe a0 d7-d0 x 0 even byte x 1 odd byte
m88 family 34/85 figure 20. an example of a typical 8-bit multiplexed bus interface micro - controller wr rd bhe ale reset ad [ 7:0 ] a [ 15:8 ] a [ 15:8 ] a [ 7:0 ] adio port port a port b port c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d ( optional ) ( optional ) m88x3fxx ai02878 table 21. 80c251 configurations configuration 80c251 read/write pins connecting to m88x3fxx flash+psd pins page mode 1 wr rd psen cntl0 cntl1 cntl2 non-page mode, 80c31 compatible a[7:0] multiplex with d[7:0} 2 wr psen only cntl0 cntl1 non-page mode a[7:0] multiplex with d[7:0} 3 wr psen only cntl0 cntl1 page mode a[15:8] multiplex with d[7:0} 4 wr rd psen cntl0 cntl1 cntl2 page mode a[15:8] multiplex with d[7:0} by the mcu via the imc buffer. see the section entitled ai/o portso, on page 39. imcs can use the address strobe to latch address bits higher than a15. any latched addresses are routed to the plds as inputs. imcs are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. figure 19 shows a typical configuration where the master mcu writes to the port a data out register. this, in turn, can be read by the slave mcu via the activation of the aslave-reado output enable product term. or to pass incoming port signals prior to driving them onto the pld input bus. the outputs of the imcs can be read by the microcontroller through the internal data bus. the enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the cpld and array or the mcu address strobe (ale/as). each product term output is used to latch or clock four imcs. port inputs 3-0 can be controlled by one product term and 7-4 by another. configurations for the imcs are specified by equations written in psdabel (see application note an1171). outputs of the imcs can be read
35/85 m88 family figure 21. an example of a typical 8-bit non-multiplexed bus interface micro - controller wr rd bhe ale reset d [ 7:0 ] a [ 15:0 ] a [ 23:16 ] d [ 7:0 ] adio port port a port b port c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d (optional) m88x3fxx ai02879 the slave can also write to the port a imcs and the master can then read the imcs directly. note that the aslave-reado and aslave-wro signals are product terms that are derived from the slave mcu inputs rd, wr, and slave_cs. microcontroller bus interface the ano-glue logico m88x3fxx flash+psd microcontroller bus interface can be directly connected to most popular microcontrollers and their control signals. key 8-bit microcontrollers with their bus types and control signals are shown in table 19. the interface type is specified using the psdsoft configuration. interfacing 16-bit mcus with two m88x3fxx flash+psd devices. the m88x3fxx flash+psd has an internal 8-bit data bus. users of 16-bit data bus mcus can connect two m88x3fxx flash+psd devices in parallel such that one is tied to the upper data byte (d15-d8) and the other is connected to the lower data byte (d7-d0). refer to m88x3fxx flash+psd application notes on the configuration of two m88x3fxx flash+psd to 16-bit mcus. m88x3fxx flash+psd interface to a multiplexed 8-bit bus figure 20 shows an example of a system using a microcontroller with an 8-bit multiplexed bus and a m88x3fxx flash+psd. the adio port on the m88x3fxx flash+psd is connected directly to the microcontroller address/data bus. ale latches the address lines internally. latched addresses can be brought out to port a or b. the m88x3fxx flash+psd drives the adio data bus only when one of its internal resources is accessed and the rd input is active. should the system address bus exceed sixteen bits, ports a, b, c, or d may be used as additional address inputs. m88x3fxx flash+psd interface to a non- multiplexed 8-bit bus figure 21 shows an example of a system using a microcontroller with an 8-bit non-multiplexed bus and a m88x3fxx flash+psd. the address bus is connected to the adio port, and the data bus is connected to port a. port a is in tri-state mode when the m88x3fxx flash+psd is not accessed by the microcontroller. should the system address bus exceed sixteen bits, ports b, c, or d may be used for additional address inputs. data byte enable reference microcontrollers have different data byte orientations. table 20 shows how the m88x3fxx flash+psd interprets byte/word operations in different bus write configurations. even-byte refers to locations with address a0 equal to zero and odd byte as locations with a0 equal to one. microcontroller interface examples figure 22 to figure 26 show examples of the basic connections between the m88x3fxx flash+psd and some popular microcontrollers. the m88x3fxx flash+psd control input pins are labeled as to the microcontroller function for which they are configured. the mcu interface is specified using the psdsoft configuration.
m88 family 36/85 figure 22. interfacing the m88x3fxx flash+psd with an 80c31 figure 23. interfacing the m88x3fxx flash+psd with the 80c251, with one read input note: 1. the a16 and a17 connections are optional. 2. in non-page-mode, ad[7:0] connects to adio[7:0]. ea/vp x1 x2 reset reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1(rd) cntl2 (psen) pd0-ale pd1 pd2 reset rd wr psen ale/p txd rxd reset 29 28 27 25 24 23 22 21 30 39 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 38 37 36 35 34 33 32 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 47 48 50 49 10 9 8 7 6 5 4 3 2 52 51 m88x3fxx 80c31 ad [ 7:0 ] ad [ 7:0 ] 21 22 23 24 25 26 27 28 17 16 29 30 a8 a9 a10 a11 a12 a13 a14 a15 rd wr psen ale 11 10 reset 20 19 18 17 14 13 12 11 ai02880 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2(psen) pd0- ale pd1 pd2 reset 32 26 43 42 41 40 39 38 37 36 24 25 27 28 29 30 31 33 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad14 ad15 ad13 ad11 ad12 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad11 ad15 ale wr a16 rd ad14 ad12 ad13 14 9 2 3 4 5 6 7 8 21 20 11 13 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/rxd p3.1/txd p3.2/int0 x2 x1 p3.3/int1 rst ea a16 1 p0.1 p0.0 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 ale psen wr rd/a16 pc0 pc1 pc3 pc4 pc5 pc6 pc7 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 80c251sb m88x3fxx reset reset 35 p3.4/t0 p3.5/t1 16 15 17 10 reset pc2 ai02881 a17 1
37/85 m88 family figure 24. interfacing the m88x3fxx flash+psd with the 80c251, with read and psen inputs figure 25. interfacing the m88x3fxx flash+psd with the 80c51x, 8-bit data bus adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2(psen) pd0- ale pd1 pd2 reset 32 26 43 42 41 40 39 38 37 36 24 25 27 28 29 30 31 33 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad14 ad15 ad13 ad11 ad12 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad11 ad15 ale wr psen rd ad14 ad12 ad13 14 9 2 3 4 5 6 7 8 21 20 11 13 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/rxd p3.1/txd p3.2/int0 x2 x1 p3.3/int1 rst ea p0.1 p0.0 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 ale psen wr rd/a16 pc0 pc1 pc3 pc4 pc5 pc6 pc7 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 80c251sb m88x3fxx reset reset 35 p3.4/t0 p3.5/t1 16 15 17 10 reset pc2 ai02882 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2 (psen) pd0-ale pd1 pd2 reset 31 33 36 2 3 4 5 43 42 41 40 39 38 37 24 25 26 27 28 29 30 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12 a13 a14 a18 a19 a17 a15 a16 a0 a1 a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12 a16 a17 a18 a19 a15 a13 a14 txd1 t2ex t2 t0 rst ea/wait busw a1 a0/wrh a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d8 a13d9 a14d10 a15d11 a16d12 a17d13 a18d14 a19d15 psen rd wrl pc0 pc1 pc3 pc4 pc5 pc6 pc7 ale psen rd wr ale 32 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 7 9 8 16 xtal1 xtal2 rxd0 txd0 rxd1 21 20 11 13 6 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 a0 a1 a2 a3 80c51xa m88x3fxx reset reset 35 17 int0 int1 14 10 15 pc2 ai02883
m88 family 38/85 80c31 figure 22 shows the interface to the 80c31, which has an 8-bit multiplexed address/data bus. the lower address byte is multiplexed with the data bus. the microcontroller control signals psen, rd, and wr may be used for accessing the internal memory components and i/o ports. the ale input (pin pd0) latches the address. 80c251 the intel 80c251 microcontroller features a user- configurable bus interface with four possible bus configurations, as shown in table 21. configuration 1 is 80c31 compatible, and the bus interface to the m88x3fxx flash+psd is identical to that shown in figure 22. configurations 2 and 3 have the same bus connection as shown in figure 23. there is only one read input (psen ) connected to the cntl1 pin on the m88x3fxx flash+psd. the a16 connection to the pa0 pin allows for a larger address input to the m88x3fxx flash+psd. configuration 4 is shown in figure 24. the rd signal is connected to cntl1 and the psen signal is connected to the cntl2. the 80c251 has two major operating modes: page mode and non-page mode. in non-page mode, the data is multiplexed with the lower address byte, and ale is active in every bus cycle. in page mode, data d[7:0] is multiplexed with address a[15:8]. in a bus cycle where there is a page hit, the ale signal is not active and only addresses a[7:0] are changing. the m88x3fxx flash+psd supports both modes. in page mode, the psd bus timing is identical to non-page mode except the address hold time and setup time with respect to ale is not required. the psd access time is measured from address a[7:0] valid to data in valid. 80c51xa the philips 80c51xa microcontroller family supports an 8- or 16-bit multiplexed bus that can figure 26. interfacing the m88x3fxx flash+psd with a 68hc11 9 10 11 12 13 14 15 16 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 (r _ w) cntl1(e) cntl 2 pd0 as pd1 pd2 reset 20 21 22 23 24 25 3 5 4 6 42 41 40 39 38 37 36 35 ad0 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a14 a15 a13 a11 a12 ad1 ad2 ad3 ad4 ad5 ad6 ad7 e as r/w xt ex reset irq xirq pa0 pa1 pa2 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 vrh vrl pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc0 pc1 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 moda e as r/w 31 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 8 7 17 19 18 34 33 32 43 44 45 46 47 48 49 50 52 51 30 29 28 27 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 7 6 5 4 3 2 52 51 modb 2 68hc11 m88x3fxx reset reset ad[7:0] ad[7:0] pc2 ai02884
39/85 m88 family figure 27. general i/o port architecture internal data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term ( .oe ) ext cs ale read mux p d b cpld-input control reg. dir reg. input macrocell enable out data in output select output mux port pin data out address ai02885 have burst cycles. address bits a[3:0] are not multiplexed, while a[19:4] are multiplexed with data bits d[15:0] in 16-bit mode. in 8-bit mode, a[11:4] are multiplexed with data bits d[7:0]. the 80c51xa can be configured to operate in eight-bit data mode. (shown in figure 25). the 80c51xa improves bus throughput and performance by executing burst cycles for code fetches. in burst mode, address a19-4 are latched internally by the m88x3fxx flash+psd, while the 80c51xa changes the a3-0 lines to fetch up to 16 bytes of code. the psd access time is then measured from address a3-a0 valid to data in valid. the psd bus timing requirement in burst mode is identical to the normal bus cycle, except the address setup and hold time with respect to ale does not apply. 68hc11 figure 26 shows an interface to a 68hc11 where the m8813f1x is configured in 8-bit multiplexed mode with e and r/w settings. the dpld can generate the read and wr signals for external devices. i/o ports there are four programmable i/o ports: ports a, b, c, and d. each of the ports is eight bits except port d, which is 3 bits. each port pin is individually user configurable, thus allowing multiple functions per port. the ports are configured using psdsoft configuration or by the microcontroller writing to on-chip registers in the csiop address space. the topics discussed in this section are: n general port architecture n port operating modes n port configuration registers n port data registers n individual port functionality. general port architecture the general architecture of the i/o port is shown in figure 27. individual port architectures are shown in figure 29 to figure 32. in general, once the purpose for a port pin has been defined, that pin will no longer be available for other purposes. exceptions will be noted.
m88 family 40/85 table 22. port operating modes note: 1. can be multiplexed with other i/o functions. table 23. port operating mode settings note: 1. n/a = not applicable 2. the direction of the port a,b, c, and d pins are controlled by the direction register ored with the individual output enable product term (.oe) from the cpld and array. 3. any of these three methods will enable jtag pins on port c. port mode port a port b port c port d mcu i/o yes yes yes yes pld i/o mcellab outputs mcellbc outputs additional ext. cs outputs pld inputs yes no no yes yes yes no yes no yes no yes no no yes yes address out yes (a7 0) yes (a7 0) or (a15 8) no no address in yes yes yes yes data port yes (d7 0) no no no peripheral i/o yes no no no jtag isp no no yes 1 no mode defined in psdabel defined in psdconfiguratio n control register setting direction register setting vm register setting jtag enable mcu i/o declare pins only n/a 1 0 1 = output, 0 = input (note 2 ) n/a n/a pld i/o logic equations n/a n/a (note 2 ) n/a n/a data port (port a) n/a specify bus type n/a n/a n/a n/a address out (port a,b) declare pins only n/a 1 1 (note 2 ) n/a n/a address in (port a,b,c,d) logic for equation input macrocells n/a n/a n/a n/a n/a peripheral i/o (port a) logic equations (psel0 & 1) n/a n/a n/a pio bit = 1 n/a jtag isp (note 3 ) jtagsel jtag configuration n/a n/a n/a jtag_enable as shown in figure 27, the ports contain an output multiplexer whose selects are driven by the configuration bits in the control registers (ports a and b only) and psdsoft configuration. inputs to the multiplexer include the following: o output data from the data out register o latched address outputs o cpld macrocell output o external chip select from cpld. the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read. the pdb is connected to the internal data bus for feedback and can be read by the microcontroller. the data out and macrocell outputs, direction and control registers, and port pin input are all connected to the pdb. the port pin's tri-state output driver enable is controlled by a two input or gate whose inputs come from the cpld and array enable product term and the direction register. if the enable
41/85 m88 family product term of any of the array outputs are not defined and that port pin is not defined as a cpld output in the psdabel file, then the direction register has sole control of the buffer that drives the port pin. the contents of these registers can be altered by the microcontroller. the pdb feedback path allows the microcontroller to check the contents of the registers. ports a, b, and c have embedded input macrocells (imcs). the imcs can be configured as latches, registers, or direct inputs to the plds. the latches and registers are clocked by the address strobe (as/ale) or a product term from the pld and array. the outputs from the imcs drive the pld input bus and can be read by the microcontroller. refer to the section entitled ainput macrocells (imcs)o, on page 33. port operating modes the i/o ports have several modes of operation. some modes can be defined using psdabel, some by the microcontroller writing to the control registers in csiop space, and some by both. the modes that can only be defined using psdsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. the modes that can be changed by the microcontroller can be done so dynamically at run- time. the pld i/o, data port, address input, and peripheral i/o modes are the only modes that must be defined before programming the device. all other modes can be changed by the microcontroller at run-time. see application note an1171 for more detail. table 22 summarizes which modes are available on each port. table 25 shows how and where the different modes are configured. each of the port operating modes are described in the following sections. mcu i/o mode in the mcu i/o mode, the microcontroller uses the m88x3fxx flash+psd ports to expand its own i/ o ports. by setting up the csiop space, the ports on the m88x3fxx flash+psd are mapped into the microcontroller address space. the addresses of the ports are listed in table 9. a port pin can be put into mcu i/o mode by writing a `0' to the corresponding bit in the control register. the mcu i/o direction may be changed by writing to the corresponding bit in the direction register, or by the output enable product term. see the section entitled adirection registero, on page 44. when the pin is configured as an output, the content of the data out register drives the pin. when configured as an input, the microcontroller can read the port input through the data in buffer. see figure 27. ports c and d do not have control registers, and are in mcu i/o mode by default. they can be used for pld i/o if equations are written for them in psdabel. pld i/o mode the pld i/o mode uses a port as an input to the cpld's input macrocells, and/or as an output from the cpld's output macrocells. the output can be tri-stated with a control signal. this output enable control signal can be defined by a product term from the pld, or by setting the corresponding bit in the direction register to `0'. the corresponding bit in the direction register must not be set to `1' if the pin is defined as a pld input pin in psdabel. table 24. i/o port latched address output assignments note: 1. n/a = not applicable. microcontroller port a (3:0) port a (7:4) port b (3:0) port b (7:4) 8051xa (8-bit) n/a 1 address (7:4) address (11:8) n/a 80c251 (page mode) n/a n/a address (11:8) address (15:12) all other 8-bit multiplexed address (3:0) address (7:4) address (3:0) address (7:4) 8-bit non-multiplexed bus n/a n/a address [3:0] address [7:4] table 25. port configuration registers note: 1. see table 29 for drive register bit definition. register name port mcu access control a,b write/read direction a,b,c,d write/read drive select 1 a,b,c,d write/read
m88 family 42/85 figure 28. peripheral i/o mode rd psel0 psel1 psel vm register bit 7 wr pa0- pa7 d0 - d7 data bus ai02886 the pld i/o mode is specified in psdabel by declaring the port pins, and then writing an equation assigning the pld i/o to a port. address out mode for microcontrollers with a multiplexed address/ data bus, address out mode can be used to drive latched addresses onto the port pins. these port pins can, in turn, drive external devices. either the output enable or the corresponding bits of both the direction register and control register must be set to a `1' for pins to use address out mode. see table 24 for the address output pin assignments on ports a and b for various mcus. for non-multiplexed 8 bit bus mode, address lines a[7:0] are available to port b in address out mode. note: do not drive address lines with address out mode to an external memory device if it is intended for the mcu to boot from the external device. the mcu must first boot from psd memory so the direction and control register bits can be set. address in mode for microcontrollers that have more than 16 address lines, the higher addresses can be connected to port a, b, c, and d. the address input can be latched in the input macrocell by the address strobe (ale/as). any input that is included in the dpld equations for the pld's flash, eeprom, or sram is considered to be an address input. table 26. port pin direction control, output enable p.t. not defined table 27. port pin direction control, output enable p.t. defined table 28. port direction assignment example direction register bit port pin mode 0 input 1 output direction register bit outpu t enable p.t. port pin mode 0 0 input 0 1 output 1 0 output 1 1 output bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000111
43/85 m88 family table 29. drive register pin assignment note: 1. na = not applicable. drive register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port a open drain open drain open drain open drain slew rate slew rate slew rate slew rate port b open drain open drain open drain open drain slew rate slew rate slew rate slew rate port c open drain open drain open drain open drain open drain open drain open drain open drain port d na na na na na slew rate slew rate slew rate data port mode port a can be used as a data bus port for a microcontroller with a non-multiplexed address/ data bus. the data port is connected to the data bus of the microcontroller. the general i/o functions are disabled in port a if the port is configured as a data port. peripheral i/o mode peripheral i/o mode can be used to interface with external peripherals. in this mode, all of port a serves as a tri-state, bi-directional data buffer for the microcontroller. peripheral i/o mode is enabled by setting bit 7 of the vm register to a `1'. figure 28 shows how port a acts as a bi- directional buffer for the microcontroller data bus if peripheral i/o mode is enabled. an equation for psel0 and/or psel1 must be written in psdabel. the buffer is tri-stated when psel 0 or 1 is not active. jtag isp port c is jtag compliant, and can be used for in- system programming (isp). you can multiplex jtag operations with other functions on port c because isp is not performed during normal system operation. for more information on the jtag port, refer to the section entitled aprogramming in-circuit using the jtag interfaceo, on page 53. port configu ration registers (pcrs) each port has a set of pcrs used for configuration. the contents of the registers can be accessed by the microcontroller through normal read/write bus cycles at the addresses given in table 9. the addresses in table 9 are the offsets in hex from the base of the csiop register. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 of its port. the three pcrs, shown in table 25, are used for setting the port configurations. the default power-up state for each register in table 25 is 00h. control register any bit set to `0' in the control register sets the corresponding port pin to mcu i/o mode, and a `1' sets it to address out mode. the default mode is mcu i/o. only ports a and b have an associated control register. table 30. port data registers register name port mcu access data in a,b,c,d read input on pin data out a,b,c,d write/read output macrocell a,b,c read outputs of macrocells write loading macrocells flip-flop mask macrocell a,b,c write/read prevents loading into a given macrocell input macrocell a,b,c read outputs of the input macrocells enable out a,b,c read the output enable control of the port driver
m88 family 44/85 figure 29. port a and port b structure internal data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term ( .oe ) ale read mux p d b cpld-input control reg. dir reg. input macrocell enable out data in output select output mux port a or b pin data out address a [ 7:0 ] or a [ 15:8 ] ai02887 direction register the direction register, in conjunction with the output enable (except for port d), controls the direction of data flow in the i/o ports. any bit set to `1' in the direction register will cause the corresponding pin to be an output, and any bit set to `0' will cause it to be an input. the default mode for all port pins is input. figure 29 and figure 31 show the port architecture diagrams for ports a/b and c, respectively. the direction of data flow for ports a, b, and c are controlled not only by the direction register, but also by the output enable product term from the pld and array. if the output enable product term is not active, the direction register has sole control of a given pin's direction. an example of a configuration for a port with the three least significant bits set to output and the remainder set to input is shown in table 28. since port d only contains three pins, the direction register for port d has only the three least significant bits active. drive select register the drive select register configures the pin driver as open drain or cmos for some port pins, and controls the slew rate for the other port pins. an external pull-up resistor should be used for pins configured as open drain. a pin can be configured as open drain if its corresponding bit in the drive select register is set to a `1'. the default pin drive is cmos. aside: the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more electrical noise. a pin operates in a high slew rate when the corresponding bit in the drive register is set to `1'. the default rate is slow slew. table 29 shows the drive register for ports a, b, c, and d. it summarizes which pins can be configured as open drain outputs and which pins the slew rate can be set for. port data registers the port data registers, shown in table 30, are used by the microcontroller to write data to or read data from the ports. table 30 shows the register name, the ports having each register type, and microcontroller access for each register type. the registers are described below. data in port pins are connected directly to the data in buffer. in mcu i/o input mode, the pin input is read through the data in buffer. data out register stores output data written by the mcu in the mcu i/o output mode. the contents of the register are
45/85 m88 family driven out to the pins if the direction register or the output enable product term is set to a1o. the contents of the register can also be read back by the microcontroller. output macrocells (omcs) the cpld omcs occupy a location in the microcontroller's address space. the microcontroller can read the output of the omcs. if the mask macrocell register bits are not set, writing to the macrocell loads data to the macrocell flip flops. refer to the section entitled aoutput macrocello, on page 29. mask macrocell register each mask register bit corresponds to an omc flip flop. when the mask register bit is set to a a1o, loading data into the omc flip flop is blocked. the default value is a0o or unblocked. input macrocells (imcs) the imcs can be used to latch or store external inputs. the outputs of the imcs are routed to the pld input bus, and can be read by the microcontroller. refer to the section entitled apldso, on page 23. enable out the enable out register can be read by the microcontroller. it contains the output enable values for a given port. a a1o indicates the driver is in output mode. a a0o indicates the driver is in tri- state and the pin is in input mode. ports a and b functionality and structure ports a and b have similar functionality and structure, as shown in figure 29. the two ports can be configured to perform one or more of the following functions: o mcu i/o mode o cpld output macrocells mcellab[7:0] can be connected to port a or port b. mcellbc[7:0] can be connected to port b or port c. o cpld input via the input macrocells. o latched address output provide latched address output per table 32. o address in additional high address inputs using the input macrocells. o open drain/slew rate pins pa[3:0] and pb[3:0] can be configured to fast slew rate, pins pa[7:4] and pb[7:4] can be configured to open drain mode. o data port port a to d[7:0] for 8 bit non- multiplexed bus o multiplexed address/data port for certain types of microcontroller interfaces. figure 30. port c structure note: 1. isp or battery back-up internal data bus data out reg. dq dq wr wr mcellbc [ 7:0 ] enable product term ( .oe ) read mux p d b cpld-input dir reg. input macrocell enable out special function 1 special function 1 configuration bit data in output select output mux port c pin data out ai02888
m88 family 46/85 figure 31. port d structure internal data bus data out reg. dq dq wr wr ecs [ 2:0 ] read mux p d b cpld-input dir reg. data in enable product term (.oe) output select output mux port d pin data out ai02889 o peripheral mode port a only port c functionality and structure port c can be configured to perform one or more of the following functions (see figure 31): o mcu i/o mode o cpld output mcellbc[7:0] outputs can be connected to port b or port c. o cpld input via the input macrocells o address in additional high address inputs using the input macrocells. o in-system programming jtag port can be enabled for programming/erase of the m88x3fxx flash+psd device. (see the section entitled aprogramming in-circuit using the jtag interfaceo, on page 53, for more information on jtag programming.) o open drain port c pins can be configured in open drain mode o battery backup features pc2 can be configured as a battery input (v stby ) pin. pc4 can be configured as a battery on indicator output pin, indicating when v cc is less than v bat . port c does not support address out mode, and therefore no control register is required. pin pc7 may be configured as the dbe input in certain microcontroller interfaces. port d functionality and structure port d has three i/o pins. see figure 32. this port does not support address out mode, and therefore no control register is required. port d can be configured to perform one or more of the following functions: o mcu i/o mode o cpld output (external chip select) o cpld input direct input to cpld, no input macrocells o slew rate pins can be set up for fast slew rate port d pins can be configured in psdsoft as input pins for other dedicated functions: o pd0 ale, as address strobe input o pd1 clkin, as clock input to the macrocells flip flops and apd counter o pd2 csi, as active low chip select input. a high input will disable the flash/eeprom/sram and csiop. external chip select the cpld also provides three chip select outputs on port d pins that can be used to select external devices. each chip select (ecs0-2) consists of one product term that can be configured active high or low. the output enable of the pin is controlled by either the output enable product term or the direction register. (see figure 32.)
47/85 m88 family figure 32. port d external chip selects pld input bus polarity bit pd2 pin pt2 ecs2 direction register polarity bit pd1 pin pt1 ecs1 enable (.oe) enable (.oe) direction register polarity bit pd0 pin pt0 ecs0 enable (.oe) direction register cpld and array ai02890 power management all m88x3fxx flash+psd devices offer configurable power saving options. these options may be used individually or in combinations, as follows: o all memory types in a psd (flash, eeprom, and sram) are built with power management technology. in addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero dc current). as soon as a transition occurs on an input, the affected memory awakes upo, changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory standby mode when no inputs are changingeit happens automatically. when using power management family devices, the pld sections can also achieve standby mode when its inputs are not changing. o like the power management feature, the automatic power down (apd) logic allows the psd to reduce to standby current automatically. the apd can also block mcu address/data signals from reaching the memories and plds. this feature is available on all the devices of the m88x3fxx flash+psd family. the apd unit is described in more detail in the section entitled aautomatic power down (apd) unit and power down modeo, on page 48. built in logic will monitor the address strobe of the mcu for activity. if there is no activity for a certain time period (mcu is asleep), the apd logic initiates power down mode (if enabled). once in power down mode, all address/data signals are blocked from reaching psd memories and plds, and the memories are deselected internally. this allows the memories and plds to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the mcu bus, etc.). keep in mind that any unblocked pld input signals that are changing table 31. power down mode's effect on ports port function pin level mcu i/o no change pld out no change address out undefined data port three-state peripheral i/o three-state
m88 family 48/85 table 32. m88 family timing and stand-by current during power down mode note: 1. power down does not affect the operation of the pld. the pld operation in this mode is based only on the turbo bit. 2. typical current consumption assuming no pld inputs are changing state and the pld turbo bit is off. mode pld propagation delay memory access time access recovery time to normal access typical stand-by current 5v v cc 3v v cc power down normal t pd (note 1 ) no access t lvdv 50 m a (note 2 )25 m a (note 2 ) figure 33. apd logic block apd en pmmr0 bit 1=1 ale reset csi clkin transition detection edge detect apd counter power down ( pdn ) disable bus interface eeprom select flash select sram select pd clr pd disable flash/eeprom/sram pld select ai02891 states keeps the pld out of standby mode, but not the memories. o the psd chip select input (csi) on all families can be used to disable the internal memories, placing them in standby mode even if inputs are changing. this feature does not block any internal signals or disable the plds. this is a good alternative to using the apd logic. there is a slight penalty in memory access time when the csi signal makes its initial transition from deselected to selected. o the pmmr registers can be written by the mcu at run-time to manage power. all three families support ablocking bitso in these registers that are set to block designated signals from reaching both plds. current consumption of the plds is directly related to the composite frequency of the changes on their inputs (see figure 36 and figure 37). significant power savings can be achieved by blocking signals that are not used in dpld or cpld logic equations. unique to the m88x3fxx flash+psd devices is the turbo bit in the pmmr0 register. this bit can be set to disable the turbo mode feature (default is turbo mode on). while turbo mode is disabled, the plds can achieve standby current when no pld inputs are changing (zero dc current). even when inputs do change, significant power can be saved at lower frequencies (ac current), compared to when turbo mode is enabled. when the turbo mode is enabled, there is a significant dc current component and the ac component is higher. automatic power down (apd) unit and power down mode the apd unit, shown in figure 33, puts the psd into power down mode by monitoring the activity of the address strobe (ale/as). if the apd unit is enabled, as soon as activity on the address strobe stops, a four bit counter starts counting. if the address strobe remains inactive for fifteen clock periods of the clkin signal, the power down (pdn) signal becomes active, and the psd will enter into power down mode, discussed next. power down mode by default, if you enable the psd apd unit, power down mode is automatically enabled. the device will enter power down mode if the address strobe (ale/as) remains inactive for fifteen clkin (pin pd1) clock periods. the following should be kept in mind when the psd is in power down mode:
49/85 m88 family figure 34. enable power down flow chart enable apd set pmmr0 bit 1 = 1 psd in power down mode ale/as idle for 15 clkin clocks? reset yes no optional disable desired inputs to pld by setting pmmr0 bits 4 and 5 and pmmr2 bits 2 through 6. ai02892 table 33. power management mode registers pmmr0 1 note: 1. the bits of this register are cleared to zero following power up. subsequent reset pulses will not clear the registers. bit 0 x 0 not used, and should be set to zero. bit 1 apd enable 0 = off automatic power down (apd) is disabled. 1 = on automatic power down (apd) is enabled. bit 2 x 0 not used, and should be set to zero. bit 3 pld turbo 0 = on pld turbo is on 1 = off pld turbo is off, saving power. bit 4 pld array clk 0=on clkin input to the pld and array is connected. every clkin change will power up the pld when turbo bit is off. 1 = off clkin input to pld and array is disconnected, saving power. bit 5 pld mcell clk 0 = on clkin input to the pld macrocells is connected. 1 = off clkin input to pld macrocells is disconnected, saving power. bit 6 x 0 not used, and should be set to zero. bit 7 x 0 not used, and should be set to zero.
m88 family 50/85 table 34. power management mode registers pmmr2 1 note: 1. the bits of this register are cleared to zero following power up. subsequent reset pulses will not clear the registers. table 35. apd counter operation bit 0 x 0 not used, and should be set to zero. bit 1 x 0 not used, and should be set to zero. bit 2 pld array cntl0 0 = on cntl0 input to the pld and array is connected. 1 = off cntl0 input to pld and array is disconnected, saving power. bit 3 pld array cntl1 0 = on cntl1 input to the pld and array is connected. 1 = off cntl1 input to pld and array is disconnected, saving power. bit 4 pld array cntl2 0 = on cntl2 input to the pld and array is connected. 1 = off cntl2 input to pld and array is disconnected, saving power. bit 5 pld array ale 0 = on ale input to the pld and array is connected. 1 = off ale input to pld and array is disconnected, saving power. bit 6 pld array dbe 0 = on dbe input to the pld and array is connected. 1 = off dbe input to pld and array is disconnected, saving power. bit 7 x 0 not used, and should be set to zero. apd enable bit ale pd polarity ale level apd counter 0 x x not counting 1 x pulsing not counting 1 1 1 counting (generates pdn after 15 clocks) 1 0 0 counting (generates pdn after 15 clocks) figure 35. reset input timing t nlnh t opr reset ai02893
51/85 m88 family table 36. chip status during reset and power down mode note: 1. the macrocell flip-flop can be cleared or set by the reset input or the pdn signal, depending on the .re and .pr equations that are defined in the psdabel file. 2. bit0 (sram_code) and bit7 (pio_en) are cleared to zero on any reset. port configuratio n reset power down mode mcu i/o input unchanged pld output active depend on inputs to pld address out tri-stated not defined data port tri-stated tri-stated peripheral i/o tri-stated tri-stated port configuratio n reset power down mode pmmr, 0 and 2 cleared (power up reset only) unchanged macrocells flip-flop unchanged 1 unchanged 1 vm register 2 initialized based on the selection in psdsoft configuration menu. unchanged all other registers cleared to a0o unchanged n if the address strobe starts pulsing again, the psd will return to normal operation. the psd will also return to normal operation if either the csi input returns low or the reset input returns high. n the mcu address/data bus is blocked from all memories and plds. n various signals can be blocked (prior to power down mode) from entering the plds by setting the appropriate bits in the pmmr registers. the blocked signals include mcu control signals and the common clock (clkin). note that blocking clkin from the plds will not block clkin from the apd unit. n all psd memories enter standby mode and are drawing standby current. however, the plds and i/o ports do not go into standby mode because you don't want to have to wait for the logic and i/o to awake-upo before their outputs can change. see table 31 for power down mode effects on psd ports. n typical standby current is 50 m a for 5 v devices, and 25 m a for 3 v devices. these standby current values assume that there are no transitions on any pld input. hc11 (or compatible) users note the hc11 turns off its e clock when it sleeps. therefore, if you are using an hc11 (or compatible) in your design, and you wish to use the power down, you must not connect the e clock to the clkin input (pd1). you should instead connect a crystal oscillator to the clkin input. the crystal oscillator frequency must be less than 15 times the frequency of as. the reason for this is that if the frequency is greater than 15 times the frequency of as, the m88x3fxx flash+psd will keep going into power down mode. other power saving options the m88x3fxx flash+psd offers other reduced power saving options that are independent of the power down mode. except for the sram standby table 37. jtag port signals port c pin jtag signals description pc0 tms mode select pc1 tck clock pc3 tstat status pc4 terr error flag pc5 tdi serial data in pc6 tdo serial data out
m88 family 52/85 table 38. jtag enable register bit 0 jtag enable 0 = off jtag port is disabled. 1 = on jtag port is enabled. bit 1 x 0 not used, and should be set to zero. bit 2 x 0 not used, and should be set to zero. bit 3 x 0 not used, and should be set to zero. bit 4 x 0 not used, and should be set to zero. bit 5 x 0 not used, and should be set to zero. bit 6 x 0 not used, and should be set to zero. bit 7 x 0 not used, and should be set to zero. and csi input features, they are enabled by setting bits in the pmmr0 and pmmr2 registers. pld power management the power and speed of the plds are controlled by the turbo bit (bit 3) in the pmmr0. by setting the bit to a1o, the turbo mode is disabled and the plds consume the specified stand-by current when the inputs are not switching for an extended time of 70 ns. the propagation delay time will be increased by 10 ns after the turbo bit is set to a1o (turned off) when the inputs change at a composite frequency of less than 15 mhz. when the turbo bit is set to a a0o (turned on), the plds run at full power and speed. the turbo bit affects the pld's d.c. power, ac power, and propagation delay. blocking mcu control signals with pmmr2 bits can further reduce pld ac power consumption. sram standby mode (battery backup) the m8813fxx flash+psd supports a battery backup operation that retains the contents of the sram in the event of a power loss. the sram has a vstby pin (pc2) that can be connected to an external battery. when v cc becomes lower than v stby then the psd will automatically connect to v stby as a power source to the sram. the sram standby current (i stby ) is typically 0.5 m a. the sram data retention voltage is 2 v minimum. the battery-on indicator (v baton )can be routed to pc4. this signal indicates when the v cc has dropped below the v stby voltage. the csi input pin pd2 of port d can be configured in psdsoft as the csi input. when low, the signal selects and enables the internal flash, eeprom, sram, and i/o for read or write operations involving the m88x3fxx flash+psd. a high on the csi pin will disable the flash memory, eeprom, and sram, and reduce the psd power consumption. however, the pld and i/o pins remain operational when csi is high. there may be a timing penalty when using the csi pin depending on the speed grade of the psd that you are using. see the timing parameter t slqv in table 53a or table 53b. input clock the m88x3fxx flash+psd provides the option to turn off the clkin input to the pld to save ac power consumption. the clkin is an input to the pld and array and the output macrocells. during power down mode, or, if the clkin input is not being used as part of the pld logic equation, the clock should be disabled to save ac power. the clkin will be disconnected from the pld and array or the macrocells by setting bits 4 or 5 to a a1o in pmmr0. input control signals the m88x3fxx flash+psd provides the option to turn off the input control signals (cntl0-2, ale, and dbe) to the pld to save ac power consumption. these control signals are inputs to the pld and array. during power down mode, or, if any of them are not being used as part of the pld logic equation, these control signals should be disabled to save ac power. they will be disconnected from the pld and array by setting bits 2, 3, 4, 5, and 6 to a a1o in the pmmr2. reset input the m88x3fxx flash+psd has an active low reset input which loads internal configurations and clears some of the registers (see table 36). figure 35 shows the reset timing requirement. the active low range has a minimum t nlnh duration. after the rising edge of reset, the m88x3fxx flash+psd remains in the reset state during the t opr range. the device must be reset at power-up, prior to use. any write operation to the eeprom is inhibited during the first 5 ms following
53/85 m88 family table 39. operating range table 40. recommended operating conditions range temperature v cc v cc tolerance 90 15 commercial 0 cto+70 c+5v 10% industrial 40 cto+85 c+5v 10% commercial 0 c to +70 c + 3 v +20/10% industrial 40 cto+85 c + 3 v +20/10% symbol parameter condition min. typ. max. unit v cc supply voltage m88x3fxy 4.5 5 5.5 v v cc supply voltage m88x3fxw 2.7 3 3.6 v power-up. while the reset input is active, the pld is active and the outputs are determined by the psdabel equations. the chip status during reset and power down mode is shown in table 36. the reset input will not abort any active programming or erase cycles in the main flash or boot block. programming in-circuit using the jtag interface the jtag interface on the m88x3fxx flash+psd can be enabled on port c (see table 37). all memory (flash and eeprom), pld logic, and psd configuration bits may be programmed through the jtag interface. a blank part can be mounted on a printed circuit board and programmed using jtag. the standard jtag signals (ieee 1149.1) are tms, tck, tdi, and tdo. two additional signals, tstat and terr, are optional jtag extensions used to speed up program and erase operations. by default, on a blank psd, four pins on port c are enabled for the basic jtag signals tms, tck, tdi, and tdo. see application note an1153 for more details on jtag in-system-programming. standard jtag signals the standard jtag signals (tms, tck, tdi, and tdo) can be enabled by any of three different conditions that are logically ored. when enabled, tdi, tdo, tck, and tms are inputs, waiting for a serial command from an external jtag controller device (such as flashlink or automated test equipment). when the enabling command is received, tdo becomes an output and the jtag channel is fully functional inside the psd. the same command that enables the jtag channel may optionally enable the two additional jtag pins, tstat and terr. the following symbolic logic equation specifies the conditions enabling the four basic jtag pins (tms, tck, tdi, and tdo) on their respective port c pins. for purposes of discussion, the logic label jtag_on will be used. when jtag_on is true, the four pins are enabled for jtag. when jtag_on is false, the four pins can be used for general psd i/o. jtag_on = psdsoft_enabled + /* an nvm configuration bit inside the psd is set by the designer in the psdsoft configuration utility. this dedicates the pins for jtag at all times (compliant with ieee 1149.1 */ microcontroller_enabled + /* the microcontroller can set a bit at run-time by writing to the psd register, jtag enable. this register is located at address csiop + offset c7h. setting the jtag_enable bit in this register will enable the pins for jtag use. this bit is cleared by a psd reset or the microcontroller. see table 38 for bit definition. */ psd_product_term_enabled; /* a dedicated product term (pt) inside the psd can be used to enable the jtag pins. this pt has the reserved name jtagsel. once defined as a node in psdabel, the designer can write an equation for jtagsel. this method is used when the port c jtag pins are multiplexed with other i/o signals. it is recommended to logically tie the node jtagsel to the jen\ signal on the flashlink cable when multiplexing jtag signals. see application note 1153 for details. */ the m88x3fxx flash+psd supports jtag in- system-configuration (isc) commands, but not boundary scan. a definition of these jtag-isc commands and sequences are defined in a supplemental document available from st. st's psdsoft software tool and flashlink jtag
m88 family 54/85 figure 36. pld i cc /frequency consumption (y versions, 5 v range) figure 37. pld i cc /frequency consumption (w versions, 3 v range) 0 10 20 30 40 60 70 80 90 100 110 v cc =5v 50 01015 52025 highest composite frequency at pld inputs (mhz) i cc (ma) turbo on (100%) turbo on (25%) turbo off turbo off pt 100% pt 25% ai02894 0 10 20 30 40 50 60 v cc =3v 01015 52025 i cc (ma) turbo on (100%) turbo on (25%) turbo off turbo off highest composite frequency at pld inputs (mhz) pt 100% pt 25% ai03100 programming cable implement these jtag-isc commands. this document is needed only as a reference for designers who use a flashlink to program their m88x3fxx flash+psd. jtag extensions tstat and terr are two jtag extension signals enabled by an aisc_enableo command received over the four standard jtag pins (tms, tck, tdi, and tdo). they are used to speed programming and erase functions by indicating status on psd pins instead of having to scan the status out serially using the standard jtag channel. see application note an1153. terr will indicate if an error has occurred when erasing a sector or programming a byte in flash memory. this signal will go low (active) when an error condition occurs, and stay low until an aisc_clearo command is executed or a chip reset pulse is received after an aisc-disableo command. terr does not apply to eeprom. tstat behaves the same as the ready/busy signal described in the section entitled athe ready/busy pin (pc3)o, on page 12. tstat will be high when the m88 family device is in read array mode (flash memory and eeprom contents can be read). tstat will be low when flash memory programming or erase cycles are in
55/85 m88 family table 41. example of m88x3fxx flash+psd typical power calculation at v cc = 5.0 v ac/dc condit ions highest composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % flash access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/182 = 24.7% turbo mode = on calculation (using typical values) i cc total = ipwrdown x %pwrdown + %normal x (i cc (ac) + i cc (dc)) = ipwrdown x %pwrdown + % normal x (%flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x 2 ma/mhz x freq pld + #pt x 400 m a/pt) =50 m a x 0.90 + 0.1 x (0.8 x 2.5 ma/mhz x 4 mhz + 0.15 x 1.5 ma/mhz x 4 mhz +2 ma/mhz x 8 mhz + 45 x 0.4 ma/pt) =45 m a + 0.1 x (8 + 0.9 + 16 + 18 ma) =45 m a + 0.1 x 42.9 =45 m a + 4.29 ma = 4.34 ma this is the operating power with no eeprom writes or flash erases. calculation is based on i out =0ma. progress, and also when data is being written to eeprom. tstat and terr can be configured as open- drain type signals during an aisc_enableo command. this facilitates a wired-or connection of tstat signals from several m88 family devices and a wired-or connection of terr signals from those same devices. this is useful when several m88 family devices are achainedo together in a jtag environment. security and flash memories and eeprom protection when the security bit is set, the device cannot be read on a device programmer or through the jtag port. when using the jtag port, only a full chip erase command is allowed. all other program/erase/verify commands are blocked. full chip erase returns the part to a non-
m88 family 56/85 table 42. example of m88x3fxx flash+psd typical power calculation at v cc = 5.0 v ac/dc condit ions highest composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % flash access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/182 = 24.7% turbo mode = off calculation (using typical values) i cc total = ipwrdown x %pwrdown + %normal x (i cc (ac) + i cc (dc)) = ipwrdown x %pwrdown + % normal x (%flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x (from graph using freq pld)) =50 m a x 0.90 + 0.1 x (0.8 x 2.5 ma/mhz x 4 mhz + 0.15 x 1.5 ma/mhz x 4 mhz + 24 ma) =45 m a + 0.1 x (8 + 0.9 + 24) =45 m a + 0.1 x 32.9 =45 m a + 3.29 ma = 3.34 ma this is the operating power with no eeprom writes or flash erases. calculation is based on i out =0ma.
57/85 m88 family table 43a. dc characteristics (5 v range) (t a = 0 to 70 c; v cc = 4.5 v to 5.5 v) note: 1. reset input has hysteresis. v il1 is valid at or below 0.2v cc 0.1. v ih1 is valid at or above 0.8v cc . 2. csi deselected or internal power down mode is active. 3. pld is in non-turbo mode, and none of the inputs are switching. 4. please see figure 36 for the pld current calculation. 5. i out =0ma symbol parameter conditions min. typ. max. unit v cc supply voltage all speeds 4.5 5 5.5 v v ih input high voltage 4.5 v < v cc <5.5v 2 v cc +0.5 v v il input low voltage 4.5 v < v cc <5.5v 0.5 0.8 v v ih1 reset high level input voltage (note 1 ) 0.8v cc v cc +0.5 v v il1 reset low level input voltage (note 1 ) 0.5 0.2v cc 0.1 v v hys reset pin hysteresis 0.3 v v lko v cc (min) for flash erase and program 3.2 4.2 v v ol output low voltage i ol =20 m a, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma, v cc = 4.5 v 0.25 0.45 v v oh output high voltage except v stby on i oh =20 m a, v cc = 4.5 v 4.4 4.49 v i oh = 2 ma, v cc = 4.5 v 2.4 3.9 v v oh1 output high voltage v stby on i oh1 =1 m av stby 0.8 v v stby sram stand-by voltage 2.0 v cc v i stby sram stand-by current v cc =0v 0.5 1 m a i idle idle current (vstby pin) v cc >v stby 0.1 0.1 m a v df sram data retention voltage only on v stby 2v i sb stand-by supply current for power down mode csi >v cc 0.3 v (notes 2,3 ) 50 200 m a i li input leakage current v ss m88 family 58/85 table 43b. dc characteristics (3 v range) (t a = 0 to 70 c; v cc = 2.7 v to 3.6 v) note: 1. reset input has hysteresis. v il1 is valid at or below 0.2v cc 0.1. v ih1 is valid at or above 0.8v cc . 2. csi deselected or internal pd is active. 3. pld is in non-turbo mode, and none of the inputs are switching. 4. please see figure 37 for the pld current calculation. 5. i out =0ma symbol parameter conditions min. typ. max. unit v cc supply voltage all speeds 2.7 3 3.6 v v ih high level input voltage 2.7 v < v cc < 3.6 v 0.7v cc v cc +0.5 v v il low level input voltage 2.7 v < v cc <3.6v 0.5 0.8 v v ih1 reset high level input voltage (note 1 ) 0.8v cc v cc +0.5 v v il1 reset low level input voltage (note 1 ) 0.5 0.2v cc 0.1 v v hys reset pin hysteresis 0.3 v v lko v cc (min) for flash erase and program 1.9 2.2 v v ol output low voltage i ol =20 m a, v cc = 2.7 v 0.01 0.1 v i ol = 4 ma, v cc = 2.7 v 0.15 0.45 v v oh output high voltage except v stby on i oh =20 m a, v cc = 2.7 v 2.9 2.99 v i oh = 1 ma, v cc = 2.7 v 2.4 2.6 v v oh1 output high voltage v stby on i oh1 =1 m av stby 0.8 v v stby sram stand-by voltage 2.0 v cc v i stby sram stand-by current v cc =0v 0.5 1 m a i idle idle current (vstby pin) v cc >v stby 0.1 0.1 m a v df sram data retention voltage only on v stby 2v i sb stand-by supply current for power down mode csi >v cc 0.3 v (notes 2,3 ) 25 100 m a i li input leakage current v ss v cc 10 510 m a i cc (dc) (note 5 ) operating supply current pld only pld_turbo = off, f = 0 mhz (note 3 ) please see figure 37 pld_turbo = on, f=0mhz 200 400 m a/pt flash or eeprom during flash or eeprom write/erase only 10 25 ma read only, f = 0 mhz 0 0 ma sram f = 0 mhz 0 0 ma i cc (ac) (note 5 ) pld ac base please see figure 37 flash or eeprom ac adder 2 2.5 ma/ mhz sram ac adder 0.8 1.5 ma/ mhz
59/85 m88 family table 44. ac symbols for pld timing example: t avlx time from address valid to ale invalid. signal letters signal behavior a address input t time c ceout output l logic level low or ale d input data h logic level high e e input v valid g internal wdog_on signal x no longer a valid logic level i interrupt input z float l ale input pw pulse width n reset input or output p port signal output q output data r wr, uds, lds, ds, iord, psen inputs s chip select input t r/w input w internal pdn signal b v stby output m output macrocell figure 38. switching waveforms key waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state ai03102
m88 family 60/85 table 45. input and output parameters 1 (t a =25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. 2. typical values are for t a =25 c and nominal supply voltages. symbol parameter test condition min. max. unit c in input capacitance (for input pins) v in =0v 4 6 pf c out output capacitance (for input/output pins) v out =0v 812pf c vpp capacitance (for cntl2/v pp )v pp =0v 18 25 pf figure 39. ac testing input output waveforms 3.0v 0v test point 1.5v ai03103 figure 40. output ac testing load circuit device under test 2.01 v 195 w c l =30pf (including scope and jig capacitance) ai03104 the following are issues concerning the parameters presented: o in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the m88x3fxx flash+psd is in each mode. also, the supply power is considerably different if the turbo bit is aoffo. o the ac power component gives the pld, eprom, and sram ma/mhz specification. figure 36 and figure 37 show the pld ma/mhz as a function of the number of product terms (pt) used. o in the pld timing parameters, add the required delay when turbo bit is aoffo. secured blank state. the security bit can be set in psdsoft configuration. all flash memory and eeprom sectors can individually be sector protected against erasures. the sector protect bits can be set in psdsoft configuration. ac/dc parameters these tables describe the ad and dc parameters of the m88 family: o dc electrical specification o ac timing specification n pld timing combinatorial timing synchronous clock mode asynchronous clock mode input macrocell timing n microcontroller timing read timing write timing peripheral mode timing power down and reset timing
61/85 m88 family table 46a. cpld combinatorial timing (5 v range) note: 1. fast slew rate output available on pa[ 3: 0], pb[ 3: 0], and pd[ 2: 0]. table 46b. cpld combinatorial timing (3 v range versions) note: 1. fast slew rate output available on pa[3:0], pb[3:0], and pd[2:0]. symbol parameter conditio ns -90 -15 fast pt aloc turbo off slew rate 1 unit min max min max t pd cpld input pin/feedback to cpld combinatorial output 25 32 add 2 add 10 sub 2 ns t ea cpld input to cpld output enable 26 32 add 10 sub 2 ns t er cpld input to cpld output disable 26 32 add 10 sub 2 ns t arp cpld register clear or preset delay 26 33 add 10 sub 2 ns t arpw cpld register clear or preset pulse width 20 29 add 10 ns t ard cpld array delay any macrocell 16 22 add 2 ns symbol parameter conditio ns -15 pt aloc turbo off slew rate 1 unit min max t pd cpld input pin/feedback to cpld combinatorial output 48 add 4 add 20 sub 6 ns t ea cpld input to cpld output enable 43 add 20 sub 6 ns t er cpld input to cpld output disable 43 add 20 sub 6 ns t arp cpld register clear or preset delay 48 add 20 sub 6 ns t arpw cpld register clear or preset pulse width 30 add 20 ns t ard cpld array delay any macrocell 29 add 4 ns figure 41. combinatorial timing pld t pd cpld input cpld output ai02899
m88 family 62/85 table 47a. cpld macrocell synchronous clock mode timing (5 v range) note: 1. fast slew rate output available on pa[ 3: 0], pb[ 3: 0], and pd[ 2: 0]. 2. clkin t clcl =t ch +t cl . table 47b. cpld macrocell synchronous clock mode timing (3 v range) note: 1. fast slew rate output available on pa[3:0], pb[3:0], and pd[2:0]. 2. clkin t clcl =t ch +t cl . symbol parameter conditions -90 -15 fast pt aloc turbo off slew rate 1 unit min max min max f max maximum frequency external feedback 1/(t s +t co ) 30.30 25.00 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co 10) 43.48 31.25 mhz maximum frequency pipelined data 1/(t ch +t cl ) 50.00 35.71 mhz t s input setup time 15 20 add 2 add 10 ns t h input hold time 0 0 ns t ch clock high time clock input 10 15 ns t cl clock low time clock input 10 15 ns t co clock to output delay clock input 18 22 sub 2 ns t ard cpld array delay any macrocell 16 22 add 2 ns t min minimum clock period 2 t ch +t cl 20 30 ns symbol parameter conditio ns -15 pt aloc turbo off slew rate 1 unit min max f max maximum frequency external feedback 1/(t s +t co ) 17.8 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co 10) 19.6 mhz maximum frequency pipelined data 1/(t ch +t cl ) 33.3 mhz t s input setup time 27 add 4 add 20 ns t h input hold time 0 ns t ch clock high time clock input 15 ns t cl clock low time clock input 15 ns t co clock to output delay clock input 35 sub 6 ns t ard cpld array delay any macrocell 29 add 4 ns t min minimum clock period 2 t ch +t cl 29 ns
63/85 m88 family figure 42. input to output disable / enable figure 43. asynchronous reset / preset figure 44. synchronous clock mode timing pld figure 45. asynchronous clock mode timing (product term clock) ter tea input input to output enable/disable ai02863 tarp register output tarpw reset/preset input ai02864 t ch t cl t co t h t s clkin input registered output ai02860 tcha tcla tcoa tha tsa clock input registered output ai02859
m88 family 64/85 table 48a. cpld macrocell asynchronou s clock mode timing (5 v range) table 48b. cpld macrocell asynchronou s clock mode timing (3 v range) symbol parameter conditions -90 -15 pt aloc turbo off slew rate unit min max min max f maxa maximum frequency external feedback 1/(t sa +t coa ) 26.32 21.27 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa 10) 35.71 27.78 mhz maximum frequency pipelined data 1/(t cha +t cla ) 41.67 35.71 mhz t sa input setup time 8 12 add 2 add 10 ns t ha input hold time 12 14 ns t cha clock input high time 12 15 add 10 ns t cla clock input low time 12 15 add 10 ns t coa clock to output delay 30 37 add 10 sub 2 ns t arda cpld array delay any macrocell 16 22 add 2 ns t mina minimum clock period 1/f cnta 28 43 ns symbol parameter conditio ns -15 pt aloc turbo off slew rate unit min max f maxa maximum frequency external feedback 1/(t sa +t coa ) 16.9 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa 10) 20.4 mhz maximum frequency pipelined data 1/(t cha +t cla ) 27 mhz t sa input setup time 12 add 4 add 20 ns t ha input hold time 15 ns t cha clock high time 22 add 20 ns t cla clock low time 15 add 20 ns t coa clock to output delay 47 add 20 sub 6 ns t ard cpld array delay any macrocell 29 add 4 ns t mina minimum clock period 1/f cnta 43 ns
65/85 m88 family table 49a. input macrocell timing (5 v range) note: 1. inputs from port a, b, and c relative to register/ latch clock from the pld. ale/ as latch timings refer to t avlx and t lxax . table 49b. input macrocell timing (3 v range) note: 1. inputs from port a, b, and c relative to register/latch clock from the pld. ale latch timings refer to t avlx and t lxax . symbol parameter conditio ns -90 -15 pt aloc turbo off unit min max min max t is input setup time (note 1 ) 00 ns t ih input hold time (note 1 ) 20 26 add 10 ns t inh nib input high time (note 1 ) 12 18 ns t inl nib input low time (note 1 ) 12 18 ns t ino nib input to combinatorial delay (note 1 ) 46 59 add 2 add 10 ns symbol parameter conditio ns -15 pt aloc turbo off unit min max t is input setup time (note 1 ) 0ns t ih input hold time (note 1 ) 30 add 20 ns t inh nib input high time (note 1 ) 13 ns t inl nib input low time (note 1 ) 13 ns t ino nib input to combinatorial delay (note 1 ) 90 add 4 add 20 ns figure 46. input macrocell timing (product term clock) t inh t inl t ino t ih t is pt clock input output ai03101
m88 family 66/85 table 50a. read timing (5 v range) note: 1. rd timing has the same timing as ds, lds, uds, and psen signals. 2. rd and psen have the same timing. 3. any input used to select an internal m88x3fxx flash+psd function. 4. in multiplexed mode, latched addresses generated from adio delay to address output on any port. 5. rd timing has the same timing as ds, lds, and uds signals. symbol parameter condi tions -90 -15 turbo off unit min max min max t lvlx ale or as pulse width 20 28 ns t avlx address setup time (note 3 ) 610 ns t lxax address hold time (note 3 ) 811 ns t avqv address valid to data valid (note 3 ) 90 150 add 10 ns t slqv cs valid to data valid 100 150 ns t rlqv rd to data valid 8-bit bus (note 5 ) 32 40 ns rd or psen to data valid 8-bit bus, 8031, 80251 (note 2 ) 38 45 ns t rhqx rd data hold time (note 1 ) 00 ns t rlrh rd pulse width (note 1 ) 32 38 ns t rhqz rd to data high-z (note 1 ) 25 30 ns t ehel e pulse width 32 38 ns t theh r/w setup time to enable 10 18 ns t eltl r/w hold time after enable 0 0 ns t avpv address input valid to address output delay (note 4 ) 25 32 ns
67/85 m88 family table 50b. read timing (3 v range) note: 1. rd timing has the same timing as ds, lds, uds, and psen signals. 2. rd and psen have the same timing for 8031. 3. any input used to select an internal m88x3fxx flash+psd function. 4. in multiplexed mode latched address generated from adio delay to address output on any port. 5. rd timing has the same timing as ds, lds, and uds signals. symbol parameter condi tions -15 turbo off unit min max t lvlx ale or as pulse width 28 ns t avlx address setup time (note 3 ) 10 ns t lxax address hold time (note 3 ) 12 ns t avqv address valid to data valid (note 3 ) 150 add 20 ns t slqv cs valid to data valid 150 ns t rlqv rd to data valid 8-bit bus (note 5 ) 35 ns rd or psen to data valid 8-bit bus, 8031, 80251 (note 2 ) 50 ns t rhqx rd data hold time (note 1 ) 0ns t rlrh rd pulse width (also ds, lds, uds) 40 ns rd or psen pulse width (8031, 80251) 55 ns t rhqz rd to data high-z (note 1 ) 45 ns t ehel e pulse width 52 ns t theh r/w setup time to enable 18 ns t eltl r/w hold time after enable 0 ns t avpv address input valid to address output delay (note 4 ) 48 ns
m88 family 68/85 figure 47. read timing note: 1. t avlx and t lxax are not required for 80c251 in page mode or 80c51xa in burst mode. t avlx t lxax 1 t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out ale/as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) e r/w ai02895
69/85 m88 family table 51a. write, erase and program timing (5 v range) note: 1. any input used to select an internal m88x3fxx flash+ps d function. 2. in multiplexed mode, latched address generated from adio delay to address output on any port. 3. wr has the same timing as e, ds, lds, uds, wrl, and wrh signals. 4. assuming data is stable before active write signal. 5. assuming write is active before data becomes valid. 6. twhax2 is the address hold time for dpld inputs that are used to generate chip selects for internal psd memory. symbol parameter condition s -90 -15 unit min. max. min. max. t lvlx ale or as pulse width 20 28 ns t avlx address setup time (note 1 ) 610ns t lxax address hold time (note 1 ) 811ns t avwl address valid to leading edge of wr (notes 1,3 ) 15 20 ns t slwl cs valid to leading edge of wr (note 3 ) 25 35 ns t dvwh wr data setup time (note 3 ) 25 53 ns t whdx wr data hold time (note 3 ) 55ns t wlwh wr pulse width (note 3 ) 35 45 ns t whax1 trailing edge of wr to address invalid (note 3 ) 88ns t whax2 trailing edge of wr to dpld address invalid (note 3,6 ) 00ns t whpv trailing edge of wr to port output valid using i/o port data register (note 3 ) 30 38 ns t dvmv data valid to port output valid using macrocell register preset/clear (notes 3,5 ) 55 65 ns t avpv address input valid to address output delay (note 2 ) 25 30 ns t wlmv wr valid to port output valid using macrocell register preset/clear (notes 3,4 ) 55 65 ns
m88 family 70/85 table 51b. write, erase and program timing (3 v range) note: 1. any input used to select an internal m88x3fxx flash+ps d function. 2. in multiplexed mode, latched address generated from adio delay to address output on any port. 3. wr has the same timing as e, ds, lds, uds, wrl, and wrh signals. 4. assuming data is stable before active write signal. 5. assuming write is active before data becomes valid. 6. twhax2 is the address hold time for dpld inputs that are used to generate chip selects for internal psd memory. symbol parameter condition s -15 unit min max t lvlx ale or as pulse width 28 t avlx address setup time (note 1 ) 10 ns t lxax address hold time (note 1 ) 12 ns t avwl address valid to leading edge of wr (notes 1,3 ) 30 ns t slwl cs valid to leading edge of wr (note 3 ) 34 ns t dvwh wr data setup time (note 3 ) 45 ns t whdx wr data hold time (note 3 ) 8ns t wlwh wr pulse width (note 3 ) 48 ns t whax1 trailing edge of wr to address invalid (note 3 ) 0ns t whax2 trailing edge of wr to dpld address invalid (note 3,6 ) 0ns t whpv trailing edge of wr to port output valid using i/o port data register (note 3 ) 45 ns t dvmv data valid to port output valid using macrocell register preset/clear (notes 3,5 ) 90 ns t avpv address input valid to address output delay (note 2 ) 48 ns t wlmv wr valid to port output valid using macrocell register preset/clear (notes 3,4 ) 90 ns
71/85 m88 family figure 48. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlmv t wlwh t dvwh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale /as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi wr (ds) e r/ w ai02896
m88 family 72/85 table 52a. program, write and erase times (5 v range) note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid tq7vqv time units before the data byte, dq0-dq7, is valid for reading. 3. if the maximum amount of time has elapsed between successive writes to an eeprom page, the transfer of this page data to ee- prom cells will begin. also, bytes cannot be written to a page any faster than the indicated minimum time. 4. these specifications are for writing a page to eeprom cells. table 52b. program, write and erase times (3 v range) note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid tq7vqv time units before the data byte, dq0-dq7, is valid for reading. 3. if this amount of time has elapsed between successive writes to an eeprom page, the transfer of this page data to eeprom cells will begin. also, bytes cannot be written to a page any faster than the indicated minimum time. 4. these specifications are for writing a page to eeprom cells. symbol parameter min. typ. max. unit flash flash program (byte) 8.5 s flash bulk erase 1 (pre-programmed to 00) 330s flash bulk erase 10 s t whqv3 sector erase (pre-programmed to 00) 1 30 s t whqv2 sector erase 2.2 s t whqv1 byte program 14 1200 m s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 m s t q7vqv q7 valid to output valid (data polling) 2 30 ns eeprom t eehwl first write protect after power up 5 ms t blc eeprom byte load cycle time 3 0.2 120 m s t wcb eeprom byte write cycle time 410ms t wcp eeprom page write cycle time 4 630ms program/erase cycles (per sector) 10,000 cycles symbol parameter min. typ. max. unit flash flash program (byte) 8.5 s flash bulk erase 1 (pre-programmed to 00) 330s flash bulk erase 10 s t whqv3 sector erase (pre-programmed to 00) 1 30 s t whqv2 sector erase 2 s t whqv1 byte program 10 1200 m s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 m s t q7vqv q7 valid to output valid (data polling) 2 ns eeprom t eehwl first write protect after power up 5 ms t blc eeprom byte load cycle time 3 0.2 120 m s t wcb eeprom byte write cycle time 410 m s t wcp eeprom page write cycle time 4 630ms program/erase cycles (per sector) 10,000 cycles
73/85 m88 family table 53a. port a peripheral data mode read timing (5 v range) table 53b. port a peripheral data mode read timing (3 v range) table 54a. port a peripheral data mode write timing (5 v range) note: 1. rd has the same timing as the ds, lds, uds, and psen signals. 2. wr has the same timing as the e, ds, lds, uds, wrl, and wrh signals. 3. any input used to select port a data peripheral mode. 4. data is already stable on port a. 5. data stable on adio pins to data on port a. symbol parameter condi tions -90 -15 turbo off unit min max min max t avqv (pa) address valid to data valid (note 3 ) 35 45 add 10 ns t slqv (pa) csi valid to data valid 35 45 add 10 ns t rlqv (pa) rd to data valid (notes 1,4 ) 32 40 ns rd to data valid 8031 mode 38 45 ns t dvqv (pa) data in to data out valid 30 38 ns t qxrh (pa) rd data hold time 0 0 ns t rlrh (pa) rd pulse width (note 1 ) 32 35 ns t rhqz (pa) rd to data high-z (note 1 ) 25 33 ns symbol parameter condi tions -15 turbo off unit min max t avqv (pa) address valid to data valid (note 3 ) 87 add 20 ns t slqv (pa) csi valid to data valid (notes 1,4 ) 70 add 20 ns rd to data valid 40 ns t rlqv (pa) rd to data valid 8031 mode 45 ns t dvqv (pa) data in to data out valid 50 ns t qxrh (pa) rd data hold time 0 ns t rlrh (pa) rd pulse width (note 1 ) 36 ns t rhqz (pa) rd to data high-z (note 1 ) 32 ns symbol parameter condition s -90 -15 unit min max min max t wlqv (pa) wr to data propagation delay (note 2 ) 35 40 ns t dvqv (pa) data to port a data propagation delay (note 5 ) 30 38 ns t whqz (pa) wr invalid to port a tri-state (note 2 ) 25 33 ns
m88 family 74/85 figure 49. peripheral i/o read timing figure 50. peripheral i/o write timing figure 51. reset timing t qxrh (pa) t rlqv ( pa) t rlrh ( pa) t dvqv ( pa) t rhqz ( pa) t slqv ( pa) t avqv (pa) address data valid ale /as a /d bus rd data on port a csi ai02897 tdvqv (pa) twlqv (pa) twhqz (pa) address data out a/d bus wr port a data out ale /as ai02898 t nlnh t opr ai02866
75/85 m88 family table 54b. port a peripheral data mode write timing (3 v range) note: 1. rd has the same timing as the ds, lds, uds, and psen signals. 2. wr has the same timing as the e, ds, lds, uds, wrl, and wrh signals. 3. any input used to select port a data peripheral mode. 4. data is already stable on port a. 5. data stable on adio pins to data on port a. table 55a. reset timing (5 v range) note: 1. reset will not reset flash or eeprom programming/erase cycles. table 55b. reset timing (3 v range) note: 1. reset will not reset flash or eeprom programming/erase cycles. table 56a. v stby(on) timing (5 v range) note: 1. v stby(on) timing is measured at v cc ramp rate of 2 ms. table 56b. v stby(on) timing (3 v range) symbol parameter conditio ns -15 unit min max t wlqv (pa) wr to data propagation delay (note 2 ) 45 ns t dvqv (pa) data to port a data propagation delay (note 5 ) 50 ns t whqz (pa) wr invalid to port a tri-state (note 2 ) 33 ns symbol parameter conditio ns min max unit t nlnh reset active low time (note 1 ) 150 ns t nlnh(po) power-on-reset active low time 1 ms t nlnh(a) warm-reset active low time 25 m s t opr reset high to operational device 120 ns symbol parameter conditio ns min max unit t nlnh reset active low time (note 1 ) 300 ns t nlnh(po) power-on-reset active low time ms t nlnh(a) warm-reset active low time m s t opr reset high to operational device 300 ns symbol parameter conditio ns min typ max unit t bvbh v stby detection to v stby on output high 20 m s t bxbl v stby off detection to v stby on output low 20 m s symbol parameter conditio ns min typ max unit t bvbh v stby detection to v stby(on) output high 2.0 m s t bxbl v stby off detection to v stby(on) output low 2.0 m s
m88 family 76/85 table 57a. isc timing (5 v range) note: 1. for anon_pldo programming, erase or in isc by-pass mode. 2. for program or erase pld only. table 57b. isc timing (3 v range) note: 1. for anon_pldo programming, erase or in isc by-pass mode. 2. for program or erase pld only. symbol parameter conditions -90 -15 unit min max min max t isccf tck clock frequency (except for pld) (note 1 ) 18 14 mhz t iscch tck clock high time (except for pld) (note 1 ) 26 31 ns t isccl tck clock low time (except for pld) (note 1 ) 26 31 ns t isccfp tck clock frequency (pld only) (note 2 ) 2 2 mhz t iscchp tck clock high time (pld only) (note 2 ) 240 240 ns t iscclp tck clock low time (pld only) (note 2 ) 240 240 ns t iscpsu isc port set up time 8 10 ns t iscph isc port hold up time 5 5 ns t iscpco isc port clock to output 23 25 ns t iscpzv isc port high-impedance to valid output 23 25 ns t iscpvz isc port valid output to high-impedance 23 25 ns symbol parameter conditions -15 unit min max t isccf tck clock frequency (except for pld) (note 1 ) 10 mhz t iscch tck clock high time (except for pld) (note 1 ) 45 ns t isccl tck clock low time (except for pld) (note 1 ) 45 ns t isccfp tck clock frequency (pld only) (note 2 ) 2 mhz t iscchp tck clock high time (pld only) (note 2 ) 240 ns t iscclp tck clock low time (pld only) (note 2 ) 240 ns t iscpsu isc port set up time 9 ns t iscph isc port hold up time 5 ns t iscpco isc port clock to output 36 ns t iscpzv isc port high-impedance to valid output 36 ns t iscpvz isc port valid output to high-impedance 36 ns
77/85 m88 family figure 52. isc timing iscch tck tdi/tms isc outputs/tdo isc outputs/tdo t isccl t iscph t iscpsu t iscpv z t iscpz v t iscpco t ai02865 table 58a. power down timing (5 v range) note: 1. t clcl is the clkin clock period. table 58b. power down timing (3 v range) note: 1. t clcl is the clkin clock period. symbol parameter condition s -90 -15 unit min max min max t lvdv ale access time from power down 90 150 ns t clwh maximum delay from apd enable to internal pdn valid signal using clkin input 15 * t clcl 1 m s symbol parameter condition s -15 unit min max t lvdv ale access time from power down 200 ns t clwh maximum delay from apd enable to internal pdn valid signal using clkin input 15 * t clcl 1 m s
m88 family 78/85 table 59. ordering information scheme note: 1. available on the 4.5 to 5.5 v range, only. 2. available on the 2.7 to 3.6 v range. example: m88 1 3 f 1 w 15 t 1 t sram capacity option 0 0 kbit t tape & reel packing 1 16 kbit flash memory capacity temperature range 3 1 mbit (128k x 8) 1 0 to 70 c 2nd non volatile memory package 1 256 kbit eeprom k plcc52 2 256 kbit flash memory t pqfp52 3 none operating voltage speed y 4.5 v to 5.5 v -90 90 ns 1 w 2.7 v to 3.6 v -15 150 ns 2 ordering information scheme when delivered from st, the m88x3fxx flash+psd device has all bits in the plds and memories in the a1o or high state. the configuration bits are in the a0o or low state. the code, configuration, and plds logic are loaded using the programming procedure. information for programming the device is available directly from st. please contact your local sales representative. the notation used for the device number is as shown in table 59. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please see the full data sheet (please consult our pages on the world wide web: www.st.com/flashpsd). alternatively, please contact your nearest st sales office.
79/85 m88 family table 60. plcc52 - 52 lead plastic leaded chip carrier, rectangular symbol mm inches typ. min. max. typ. min. max. a 4.19 4.57 0.165 0.180 a1 2.54 2.79 0.100 0.110 a2 0.91 0.036 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 c 0.246 0.261 0.0097 0.0103 d 19.94 20.19 0.785 0.795 d1 19.05 19.15 0.750 0.754 d2 17.53 18.54 0.690 0.730 e 19.94 20.19 0.785 0.795 e1 19.05 19.15 0.750 0.754 e2 17.53 18.54 0.690 0.730 e 1.27 0.050 f 0.00 0.25 0.000 0.010 r 0.89 0.035 n52 52 nd 13 13 ne 13 13 cp 0.10 0.004 figure 53. plcc52 (k) note: 1. drawing is not to scale. plcc-b d ne e1 e 1n d1 nd cp b d2/e2 e b1 a1 a r c 1.14 (.045) f a2
m88 family 80/85 table 61. pin assignments plcc52 pin no. pin assignments pin no. pin assignments 1 gnd 27 pa2 2 pb5 28 pa1 3 pb4 29 pa0 4 pb3 30 ad0 5 pb2 31 ad1 6 pb1 32 ad2 7 pb0 33 ad3 8 pd2 34 ad4 9 pd1 35 ad5 10 pd0 36 ad6 11 pc7 37 ad7 12 pc6 38 v cc 13 pc5 39 ad8 14 pc4 40 ad9 15 v cc 41 ad10 16 gnd 42 ad11 17 pc3 43 ad12 18 pc2 (v stby ) 44 ad13 19 pc1 45 ad14 20 pc0 46 ad15 21 pa7 47 cntl0 22 pa6 48 reset 23 pa5 49 cntl2 24 pa4 50 cntl1 25 pa3 51 pb7 26 gnd 52 pb6
81/85 m88 family table 62. pqfp52 - 52 lead plastic quad flatpack symb. mm inches typ. min. max. typ. min. max. a 2.45 0.096 a1 0.25 0.010 a2 2.00 1.80 2.20 0.079 0.071 0.087 b 0.22 0.40 0.009 0.016 c 0.11 0.23 0.004 0.009 d 13.20 12.95 13.45 0.520 0.510 0.530 d1 10.00 9.80 10.20 0.394 0.386 0.402 d2 7.80 0.307 e 13.20 12.95 13.45 0.520 0.510 0.530 e1 10.00 9.80 10.20 0.394 0.386 0.402 e2 7.80 0.307 e 0.65 0.026 l 0.88 0.73 1.03 0.035 0.029 0.041 l1 1.60 0.063 a 0 7 0 7 n52 52 nd 13 13 ne 13 13 cp 0.10 0.004 figure 54. pqfp52 (t) note: 1. drawing is not to scale. qfp nd e1 cp b e a2 a n l a1 a d1 d 1 e ne c d2 e2 l1
m88 family 82/85 table 63. pin assignments pqfp52 pin no. pin assignments pin no. pin assignments 1 pd2 27 ad4 2 pd1 28 ad5 3 pd0 29 ad6 4 pc7 30 ad7 5pc6 31 v cc 6 pc5 32 ad8 7 pc4 33 ad9 8 v cc 34 ad10 9 gnd 35 ad11 10 pc3 36 ad12 11 pc2 37 ad13 12 pc1 38 ad14 13 pc0 39 ad15 14 pa7 40 cntl0 15 pa6 41 reset 16 pa5 42 cntl2 17 pa4 43 cntl1 18 pa3 44 pb7 19 gnd 45 pb6 20 pa2 46 gnd 21 pa1 47 pb5 22 pa0 48 pb4 23 ad0 49 pb3 24 ad1 50 pb2 25 ad2 51 pb1 26 ad3 52 pb0
83/85 m88 family table of contents description . . . . . . . . . . . . . . . . ..... ............... ......... ...................... page 2 key features . . . . . . . ........................................................... page 4 general information . ................................................... ........ page 5 m88x3fxx flash+psd family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................... page5 m88x3fxx flash+psd architectural overview . . . ...................................page5 development system . . . . .......... ........................ ..................... page 8 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................. ..........page11 m88x3fxx flash+psd register description and address offset . . . . . . . . . . . . . . . . . . . . . . . page 11 m88 family functional blocks . . . . . . . . . . . . . . . . . .................................. page 12 memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......... ..... page 12 plds ....................................................................page23 microcontroller bus interface . . . . . . . . . ......................................... page 35 i/oports .................................................................. page 39 power management . . . .................................................... .. page 47 programming in-circuit using the jtag interface . ................................. page 53 ac/dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... page 60 ordering information scheme . . . . . . . . . . . . . . ...................................... page 78
m88 family 84/85 table 64. revision history date description of revision 11-jan-2000 document written
85/85 m88 family information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a . http://www.st.com

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